[llvm] [AArch64] Update zero latency instructions in Neoverse scheduling tables (PR #165690)

[Ricardo Jesus via llvm-commits]

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@@ -882,7 +906,7 @@ def : SchedAlias<WriteFImm, N2Write_2c_1V>;
 def : InstRW<[N2Write_2c_1V], (instrs FMOVHr, FMOVSr, FMOVDr)>;
 
 // FP transfer, from gen to low half of vec reg
-def : InstRW<[N2Write_3c_1M0], (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr,
+def : InstRW<[N2Write_0or3c_1M0], (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr,
                                         FMOVHWr, FMOVHXr, FMOVSWr, FMOVDXr)>;
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rj-jesus wrote:

Thanks, based on the SWOG it looks like the throughput may now be slightly higher than advertised? The new change still looks better than before, so up to you if you want to follow up with a fix.

https://github.com/llvm/llvm-project/pull/165690