[llvm] [AArch64] Update zero latency instructions in Neoverse scheduling tables (PR #165690)

[Ricardo Jesus via llvm-commits]

rj-jesus wrote:

> It looks like these zero-latency instructions still take up decode resources, which we don’t currently describe explicitly.
But the work done is largely register renaming, and there are no micro-ops dispatched to the individual pipelines.

I believe we implicitly model decode constraints in the "IssueWidth". My main concern with modelling these instructions with zero micro-ops is that it might trick the machine scheduler into assuming they can be scheduled freely, which AFAIU isn't true. Also, OP_RETIRED suggests these instructions do count as a micro-op.

Do you have any performance data that suggests this is preferable for performance or at least neutral?

https://github.com/llvm/llvm-project/pull/165690