[llvm] [RISCV][llvm] Preliminary P extension codegen support (PR #162668)

Brandon Wu via llvm-commits llvm-commits at lists.llvm.org
Tue Nov 4 21:58:16 PST 2025


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@@ -10426,6 +10530,26 @@ SDValue RISCVTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
     return DAG.getNode(RISCVISD::FMV_H_X, DL, EltVT, IntExtract);
   }
 
+  if (Subtarget.enablePExtCodeGen() && VecVT.isFixedLengthVector()) {
+    if (VecVT != MVT::v4i16 && VecVT != MVT::v2i16 && VecVT != MVT::v8i8 &&
+        VecVT != MVT::v4i8 && VecVT != MVT::v2i32)
+      return SDValue();
+    SDValue Extracted = DAG.getBitcast(XLenVT, Vec);
+    unsigned ElemWidth = EltVT.getSizeInBits();
+    if (auto *IdxC = dyn_cast<ConstantSDNode>(Idx)) {
----------------
4vtomat wrote:

You are right, it's getting folded!

https://github.com/llvm/llvm-project/pull/162668


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