[llvm] [RISCV][llvm] Preliminary P extension codegen support (PR #162668)

[Craig Topper via llvm-commits]

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@@ -79,6 +79,32 @@ static void generateInstSeqImpl(int64_t Val, const MCSubtargetInfo &STI,
     }
   }
 
+  if (STI.hasFeature(RISCV::FeatureStdExtP)) {
+    // Check if the immediate is packed i8 or i10
+    int32_t Bit63To32 = Val >> 32;
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topperc wrote:

This is a signed shift which will replicate bit 63 to bits 63:32. If the value is negative it will never match `Bit31To0` since that always has zeros in bits 63:32.

https://github.com/llvm/llvm-project/pull/162668