[llvm] [RISCV][llvm] Preliminary P extension codegen support (PR #162668)

[Craig Topper via llvm-commits]

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@@ -1034,6 +1034,14 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
     if (!isInt<32>(Imm) && isUInt<32>(Imm) && hasAllWUsers(Node))
       Imm = SignExtend64<32>(Imm);
 
+    if (hasAllWUsers(Node) && Subtarget->hasStdExtP() &&
+        Subtarget->enablePExtCodeGen()) {
+      // If its 4 packed 8 bit integer or 2 packed signed integer, we can simply
+      // copy lower 32 bits to higher 32 bits to make it able to rematerialize
+      // to PLI_B or PLI_H
+      Imm = (Imm << 32) | (Imm & 0xFFFFFFFF);
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topperc wrote:

Left shifting a signed immediate is undefined behavior if it ends up changing the sign. You may need a cast to (uint64_t) before the shift.

This is only profitable if the constant can use PLI right? This looks like it would change a lot of other constants. Especially constants that are simm12 already.

https://github.com/llvm/llvm-project/pull/162668