[llvm] [AArch64][GlobalISel] Improve lowering of vector fp16 fptrunc (PR #163398)

[David Green via llvm-commits]

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@@ -8486,8 +8488,31 @@ LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) {
   assert(MRI.getType(Dst).getScalarType() == LLT::scalar(16) &&
          MRI.getType(Src).getScalarType() == LLT::scalar(64));
 
-  if (MRI.getType(Src).isVector()) // TODO: Handle vectors directly.
-    return UnableToLegalize;
+  if (MRI.getType(Src).isVector()) {
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davemgreen wrote:

I think it is worth checking that the FPTruncOdd is legal can be legalized, to help not produce them on architectures that do not have the instructions.

https://github.com/llvm/llvm-project/pull/163398