[llvm] [AArch64][GlobalISel] Improve lowering of vector fp16 fptrunc (PR #163398)

[David Green via llvm-commits]

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@@ -8486,8 +8488,31 @@ LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) {
   assert(MRI.getType(Dst).getScalarType() == LLT::scalar(16) &&
          MRI.getType(Src).getScalarType() == LLT::scalar(64));
 
-  if (MRI.getType(Src).isVector()) // TODO: Handle vectors directly.
-    return UnableToLegalize;
+  if (MRI.getType(Src).isVector()) {
+    Register Dst = MI.getOperand(0).getReg();
+    Register Src = MI.getOperand(1).getReg();
+    LLT DstTy = MRI.getType(Dst);
+    LLT SrcTy = MRI.getType(Src);
+
+    LLT MidTy = LLT::fixed_vector(SrcTy.getNumElements(), LLT::scalar(32));
+
+    MachineInstrBuilder Mid;
+    MachineInstrBuilder Fin;
+    MIRBuilder.setInstrAndDebugLoc(MI);
+    switch (MI.getOpcode()) {
+    default:
+      return UnableToLegalize;
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davemgreen wrote:

When is this not G_FPTRUNC?

https://github.com/llvm/llvm-project/pull/163398