[llvm] [AMDGPU] Add regbankselect rules for G_ADD/SUB and variants (PR #159860)

[Anshil Gandhi via llvm-commits]

================
@@ -345,6 +346,25 @@ void AMDGPURegBankLegalizeCombiner::tryCombineS1AnyExt(MachineInstr &MI) {
   llvm_unreachable("missing anyext + trunc combine");
 }
 
+void AMDGPURegBankLegalizeCombiner::tryCombineTrunc(MachineInstr &MI) {
+  if (MI.getOpcode() != AMDGPU::G_TRUNC)
+    return;
+
+  Register Dst = MI.getOperand(0).getReg();
+  Register Src = MI.getOperand(1).getReg();
+  auto *SrcDefMI = MRI.getVRegDef(Src);
+  if (MRI.getType(Dst) != LLT::scalar(1) || !MRI.use_empty(Dst))
+    return;
+
+  if (SrcDefMI && (SrcDefMI->getOpcode() == AMDGPU::G_UADDO ||
+                   SrcDefMI->getOpcode() == AMDGPU::G_USUBO ||
+                   SrcDefMI->getOpcode() == AMDGPU::G_UADDE ||
+                   SrcDefMI->getOpcode() == AMDGPU::G_USUBE)) {
+    MI.eraseFromParent();
+    return;
+  }
+}
+
----------------
gandhi56 wrote:

I realize checking the opcodes is not necessary so I got rid of them.

I implemented this as part of the cleanup loop because your suggestion to implement it as part of the mapping of Sgpr32Trunc expectedly avoided emitting `G_TRUNC`. I am okay with not emitting `G_TRUNC` in the first place if it has no uses. Should I revert to that change?

https://github.com/llvm/llvm-project/pull/159860