[llvm] [AMDGPU] Add regbankselect rules for G_ADD/SUB and variants (PR #159860)

[Petar Avramovic via llvm-commits]

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@@ -345,6 +346,25 @@ void AMDGPURegBankLegalizeCombiner::tryCombineS1AnyExt(MachineInstr &MI) {
   llvm_unreachable("missing anyext + trunc combine");
 }
 
+void AMDGPURegBankLegalizeCombiner::tryCombineTrunc(MachineInstr &MI) {
+  if (MI.getOpcode() != AMDGPU::G_TRUNC)
+    return;
+
+  Register Dst = MI.getOperand(0).getReg();
+  Register Src = MI.getOperand(1).getReg();
+  auto *SrcDefMI = MRI.getVRegDef(Src);
+  if (MRI.getType(Dst) != LLT::scalar(1) || !MRI.use_empty(Dst))
+    return;
+
+  if (SrcDefMI && (SrcDefMI->getOpcode() == AMDGPU::G_UADDO ||
+                   SrcDefMI->getOpcode() == AMDGPU::G_USUBO ||
+                   SrcDefMI->getOpcode() == AMDGPU::G_UADDE ||
+                   SrcDefMI->getOpcode() == AMDGPU::G_USUBE)) {
+    MI.eraseFromParent();
+    return;
+  }
+}
+
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petar-avramovic wrote:

This is way too specific what is so special with G_UADDO etc, also not a combine it just deletes MI. What was wrong with my earlier suggestion?
Should write tests with proper sgpr S1 use
And not insert Trunc to Sgpr S1 if there is no use

https://github.com/llvm/llvm-project/pull/159860