[llvm] [AMDGPU] Support image atomic no return instructions (PR #150742)

[Mirko Brkušanin via llvm-commits]

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@@ -6720,9 +6720,17 @@ bool AMDGPULegalizerInfo::legalizeImageIntrinsic(
   // We are only processing the operands of d16 image operations on subtargets
   // that use the unpacked register layout, or need to repack the TFE result.
 
+  unsigned IntrOpcode = Intr->BaseOpcode;
+  // For image atomic: use no-return opcode if result is unused.
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mbrkusanin wrote:

Only effect that this has is that it changes opcode from `G_AMDGPU_INTRIN_IMAGE_LOAD` to `G_AMDGPU_INTRIN_IMAGE_LOAD_NORET` which is not appropriate since we do not have "`noret`" image atomic intrinsics (this patch does not add them) and MachineInstr still has a return value at this point.

If you are not removing def operand here then you should not make any other change either. Real transformation happens in instruction selection (where we pick _noret opcode, set cpol bit and remove def operand).

Even check below for `AMDGPU::IMAGE_ATOMIC_PK_ADD_F16_NORTN` and `AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16_NORTN` opcodes is unnecessary because `*ATOMIC*_NORTN` opcodes will not show up at this point in legalizer.

Your SelectionDAG changes are only in `SITargetLowering::lowerImage` which is instruction selection. So you can remove all changes from `AMDGPULegalizerInfo.cpp` to keep it consistent between SDag and GlobalISel.

https://github.com/llvm/llvm-project/pull/150742