[llvm] [AMDGPU] Support image atomic no return instructions (PR #150742)

[Harrison Hao via llvm-commits]

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@@ -6720,9 +6720,17 @@ bool AMDGPULegalizerInfo::legalizeImageIntrinsic(
   // We are only processing the operands of d16 image operations on subtargets
   // that use the unpacked register layout, or need to repack the TFE result.
 
+  unsigned IntrOpcode = Intr->BaseOpcode;
+  // For image atomic: use no-return opcode if result is unused.
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harrisonGPU wrote:

Okay, my understanding is that `SIISelLowering.cpp` and `AMDGPULegalizerInfo.cpp` have the same logic for `IsAtomicPacked16Bit`. If I change `SIISelLowering.cpp`, I’ll need to update `AMDGPULegalizerInfo.cpp` at the same time. What do you think?

https://github.com/llvm/llvm-project/pull/150742