[llvm] 6762cfe - [RISCV] Remove duplicate Zvfbfmin patterns that use base Zve instructions. (#164110)

[via llvm-commits]

Author: Craig Topper
Date: 2025-10-19T17:09:14Z
New Revision: 6762cfe9d534f1cf7c6de3836c4644abe929474e

URL: https://github.com/llvm/llvm-project/commit/6762cfe9d534f1cf7c6de3836c4644abe929474e
DIFF: https://github.com/llvm/llvm-project/commit/6762cfe9d534f1cf7c6de3836c4644abe929474e.diff

LOG: [RISCV] Remove duplicate Zvfbfmin patterns that use base Zve instructions. (#164110)

These patterns already exist in our other V extension files using
AllFloatAndBF16Vectors without Zvfbfmin predicate. Which is good because
we need them for Zvfbfa without depending on Zvfbfmin.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
index 32bc63c482ed2..85700aea94592 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
@@ -439,28 +439,8 @@ let Predicates = [HasStdExtZvfbfmin] in {
                   fvti.AVL, fvti.Log2SEW, TA_MA)>;
   }
 
-  defm : VPatUnaryV_V_AnyMask<"int_riscv_vcompress", "PseudoVCOMPRESS", AllBF16Vectors>;
-  defm : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER",
-                                  AllBF16Vectors, uimm5>;
-  defm : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16",
-                                eew=16, vtilist=AllBF16Vectors>;
-  defm : VPatTernaryV_VX_VI<"int_riscv_vslideup", "PseudoVSLIDEUP", AllBF16Vectors, uimm5>;
-  defm : VPatTernaryV_VX_VI<"int_riscv_vslidedown", "PseudoVSLIDEDOWN", AllBF16Vectors, uimm5>;
-
   foreach fvti = AllBF16Vectors in {
-    defm : VPatBinaryCarryInTAIL<"int_riscv_vmerge", "PseudoVMERGE", "VVM",
-                                 fvti.Vector,
-                                 fvti.Vector, fvti.Vector, fvti.Mask,
-                                 fvti.Log2SEW, fvti.LMul, fvti.RegClass,
-                                 fvti.RegClass, fvti.RegClass>;
-
     defvar ivti = GetIntVTypeInfo<fvti>.Vti;
-    def : Pat<(fvti.Vector (vselect (fvti.Mask VMV0:$vm), fvti.RegClass:$rs1,
-                                                          fvti.RegClass:$rs2)),
-              (!cast<Instruction>("PseudoVMERGE_VVM_"#fvti.LMul.MX)
-                   (fvti.Vector (IMPLICIT_DEF)),
-                   fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask VMV0:$vm),
-                   fvti.AVL, fvti.Log2SEW)>;
 
     def : Pat<(fvti.Vector (vselect (fvti.Mask VMV0:$vm),
                                     (SplatFPOp (SelectScalarFPAsInt (XLenVT GPR:$imm))),
@@ -476,15 +456,6 @@ let Predicates = [HasStdExtZvfbfmin] in {
                    (fvti.Vector (IMPLICIT_DEF)),
                    fvti.RegClass:$rs2, 0, (fvti.Mask VMV0:$vm), fvti.AVL, fvti.Log2SEW)>;
 
-    def : Pat<(fvti.Vector (riscv_vmerge_vl (fvti.Mask VMV0:$vm),
-                                            fvti.RegClass:$rs1,
-                                            fvti.RegClass:$rs2,
-                                            fvti.RegClass:$passthru,
-                                            VLOpFrag)),
-              (!cast<Instruction>("PseudoVMERGE_VVM_"#fvti.LMul.MX)
-                   fvti.RegClass:$passthru, fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask VMV0:$vm),
-                   GPR:$vl, fvti.Log2SEW)>;
-
     def : Pat<(fvti.Vector (riscv_vmerge_vl (fvti.Mask VMV0:$vm),
                                             (SplatFPOp (SelectScalarFPAsInt (XLenVT GPR:$imm))),
                                             fvti.RegClass:$rs2,
@@ -503,32 +474,6 @@ let Predicates = [HasStdExtZvfbfmin] in {
               (!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX)
                    fvti.RegClass:$passthru, fvti.RegClass:$rs2, 0, (fvti.Mask VMV0:$vm),
                    GPR:$vl, fvti.Log2SEW)>;
-
-    def : Pat<(fvti.Vector
-               (riscv_vrgather_vv_vl fvti.RegClass:$rs2,
-                                     (ivti.Vector fvti.RegClass:$rs1),
-                                     fvti.RegClass:$passthru,
-                                     (fvti.Mask VMV0:$vm),
-                                     VLOpFrag)),
-              (!cast<Instruction>("PseudoVRGATHER_VV_"# fvti.LMul.MX#"_E"# fvti.SEW#"_MASK")
-                   fvti.RegClass:$passthru, fvti.RegClass:$rs2, fvti.RegClass:$rs1,
-                   (fvti.Mask VMV0:$vm), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>;
-    def : Pat<(fvti.Vector (riscv_vrgather_vx_vl fvti.RegClass:$rs2, GPR:$rs1,
-                                                fvti.RegClass:$passthru,
-                                                (fvti.Mask VMV0:$vm),
-                                                VLOpFrag)),
-              (!cast<Instruction>("PseudoVRGATHER_VX_"# fvti.LMul.MX#"_MASK")
-                   fvti.RegClass:$passthru, fvti.RegClass:$rs2, GPR:$rs1,
-                   (fvti.Mask VMV0:$vm), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>;
-    def : Pat<(fvti.Vector
-               (riscv_vrgather_vx_vl fvti.RegClass:$rs2,
-                                     uimm5:$imm,
-                                     fvti.RegClass:$passthru,
-                                     (fvti.Mask VMV0:$vm),
-                                     VLOpFrag)),
-              (!cast<Instruction>("PseudoVRGATHER_VI_"# fvti.LMul.MX#"_MASK")
-                   fvti.RegClass:$passthru, fvti.RegClass:$rs2, uimm5:$imm,
-                   (fvti.Mask VMV0:$vm), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>;
   }
 }