[llvm] aa70f66 - [RISCV] Remove vfmerge isel patterns under Zvfbfmin predicate. (#164105)

[via llvm-commits]

Author: Craig Topper
Date: 2025-10-19T09:27:39-07:00
New Revision: aa70f66fe2405a0fb33c79d2027627312b27efc2

URL: https://github.com/llvm/llvm-project/commit/aa70f66fe2405a0fb33c79d2027627312b27efc2
DIFF: https://github.com/llvm/llvm-project/commit/aa70f66fe2405a0fb33c79d2027627312b27efc2.diff

LOG: [RISCV] Remove vfmerge isel patterns under Zvfbfmin predicate. (#164105)

vfmerge isn't a valid instruction for Zvfbfmin. These look to have been
mistakenly added as part of Zvfbfa.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
index 9358486c13da2..32bc63c482ed2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
@@ -453,19 +453,6 @@ let Predicates = [HasStdExtZvfbfmin] in {
                                  fvti.Vector, fvti.Vector, fvti.Mask,
                                  fvti.Log2SEW, fvti.LMul, fvti.RegClass,
                                  fvti.RegClass, fvti.RegClass>;
-    defm : VPatBinaryCarryInTAIL<"int_riscv_vfmerge", "PseudoVFMERGE",
-                                 "V"#fvti.ScalarSuffix#"M",
-                                 fvti.Vector,
-                                 fvti.Vector, fvti.Scalar, fvti.Mask,
-                                 fvti.Log2SEW, fvti.LMul, fvti.RegClass,
-                                 fvti.RegClass, fvti.ScalarRegClass>;
-    defvar instr = !cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX);
-    def : Pat<(fvti.Vector (int_riscv_vfmerge (fvti.Vector fvti.RegClass:$passthru),
-                                              (fvti.Vector fvti.RegClass:$rs2),
-                                              (fvti.Scalar (fpimm0)),
-                                              (fvti.Mask VMV0:$vm), VLOpFrag)),
-              (instr fvti.RegClass:$passthru, fvti.RegClass:$rs2, 0,
-                     (fvti.Mask VMV0:$vm), GPR:$vl, fvti.Log2SEW)>;
 
     defvar ivti = GetIntVTypeInfo<fvti>.Vti;
     def : Pat<(fvti.Vector (vselect (fvti.Mask VMV0:$vm), fvti.RegClass:$rs1,
@@ -489,15 +476,6 @@ let Predicates = [HasStdExtZvfbfmin] in {
                    (fvti.Vector (IMPLICIT_DEF)),
                    fvti.RegClass:$rs2, 0, (fvti.Mask VMV0:$vm), fvti.AVL, fvti.Log2SEW)>;
 
-    def : Pat<(fvti.Vector (vselect (fvti.Mask VMV0:$vm),
-                                    (SplatFPOp fvti.ScalarRegClass:$rs1),
-                                    fvti.RegClass:$rs2)),
-              (!cast<Instruction>("PseudoVFMERGE_V"#fvti.ScalarSuffix#"M_"#fvti.LMul.MX)
-                   (fvti.Vector (IMPLICIT_DEF)),
-                   fvti.RegClass:$rs2,
-                   (fvti.Scalar fvti.ScalarRegClass:$rs1),
-                   (fvti.Mask VMV0:$vm), fvti.AVL, fvti.Log2SEW)>;
-
     def : Pat<(fvti.Vector (riscv_vmerge_vl (fvti.Mask VMV0:$vm),
                                             fvti.RegClass:$rs1,
                                             fvti.RegClass:$rs2,
@@ -526,16 +504,6 @@ let Predicates = [HasStdExtZvfbfmin] in {
                    fvti.RegClass:$passthru, fvti.RegClass:$rs2, 0, (fvti.Mask VMV0:$vm),
                    GPR:$vl, fvti.Log2SEW)>;
 
-    def : Pat<(fvti.Vector (riscv_vmerge_vl (fvti.Mask VMV0:$vm),
-                                            (SplatFPOp fvti.ScalarRegClass:$rs1),
-                                            fvti.RegClass:$rs2,
-                                            fvti.RegClass:$passthru,
-                                            VLOpFrag)),
-              (!cast<Instruction>("PseudoVFMERGE_V"#fvti.ScalarSuffix#"M_"#fvti.LMul.MX)
-                   fvti.RegClass:$passthru, fvti.RegClass:$rs2,
-                   (fvti.Scalar fvti.ScalarRegClass:$rs1),
-                   (fvti.Mask VMV0:$vm), GPR:$vl, fvti.Log2SEW)>;
-
     def : Pat<(fvti.Vector
                (riscv_vrgather_vv_vl fvti.RegClass:$rs2,
                                      (ivti.Vector fvti.RegClass:$rs1),