[llvm] [PowerPC] Remove NoInfsFPMath uses (PR #163029)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 16 17:58:11 PDT 2025
https://github.com/paperchalice updated https://github.com/llvm/llvm-project/pull/163029
>From f6bb2d4ebd9e63d9a3df339614e16888c6579ac2 Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Sun, 12 Oct 2025 09:43:43 +0800
Subject: [PATCH] [PowerPC] Remove NoInfsFPMath uses
---
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 2 +-
llvm/test/CodeGen/PowerPC/change-no-infs.ll | 67 -------
llvm/test/CodeGen/PowerPC/fsel.ll | 195 +++++++++++++-------
llvm/test/CodeGen/PowerPC/scalar-equal.ll | 110 ++++-------
4 files changed, 160 insertions(+), 214 deletions(-)
delete mode 100644 llvm/test/CodeGen/PowerPC/change-no-infs.ll
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 8bf0d118da575..9d5ea40c27fde 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -8313,7 +8313,7 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
// general, fsel-based lowering of select is a finite-math-only optimization.
// For more information, see section F.3 of the 2.06 ISA specification.
// With ISA 3.0
- if ((!DAG.getTarget().Options.NoInfsFPMath && !Flags.hasNoInfs()) ||
+ if (!Flags.hasNoInfs() ||
(!DAG.getTarget().Options.NoNaNsFPMath && !Flags.hasNoNaNs()) ||
ResVT == MVT::f128)
return Op;
diff --git a/llvm/test/CodeGen/PowerPC/change-no-infs.ll b/llvm/test/CodeGen/PowerPC/change-no-infs.ll
deleted file mode 100644
index 0cd5eb5408e3e..0000000000000
--- a/llvm/test/CodeGen/PowerPC/change-no-infs.ll
+++ /dev/null
@@ -1,67 +0,0 @@
-; Check that we can enable/disable NoInfsFPMath and NoNaNsInFPMath via function
-; attributes. An attribute on one function should not magically apply to the
-; next one.
-
-; RUN: llc < %s -mtriple=powerpc64-unknown-unknown -mcpu=pwr7 -mattr=-vsx \
-; RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=SAFE
-
-; RUN: llc < %s -mtriple=powerpc64-unknown-unknown -mcpu=pwr7 -mattr=-vsx \
-; RUN: -enable-no-infs-fp-math -enable-no-nans-fp-math \
-; RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=UNSAFE
-
-; The fcmp+select in these functions should be converted to a fsel instruction
-; when both NoInfsFPMath and NoNaNsInFPMath are enabled.
-
-; CHECK-LABEL: default0:
-define double @default0(double %a, double %y, double %z) {
-entry:
-; SAFE-NOT: fsel
-; UNSAFE: fsel
- %cmp = fcmp ult double %a, 0.000000e+00
- %z.y = select i1 %cmp, double %z, double %y
- ret double %z.y
-}
-
-; CHECK-LABEL: unsafe_math_off:
-define double @unsafe_math_off(double %a, double %y, double %z) #0 #2 {
-entry:
-; SAFE-NOT: fsel
-; UNSAFE-NOT: fsel
- %cmp = fcmp ult double %a, 0.000000e+00
- %z.y = select i1 %cmp, double %z, double %y
- ret double %z.y
-}
-
-; CHECK-LABEL: default1:
-define double @default1(double %a, double %y, double %z) {
-; SAFE-NOT: fsel
-; UNSAFE: fsel
- %cmp = fcmp ult double %a, 0.000000e+00
- %z.y = select i1 %cmp, double %z, double %y
- ret double %z.y
-}
-
-; CHECK-LABEL: unsafe_math_on:
-define double @unsafe_math_on(double %a, double %y, double %z) #1 #3 {
-entry:
-; SAFE-NOT: fsel
-; UNSAFE-NOT: fsel
- %cmp = fcmp ult double %a, 0.000000e+00
- %z.y = select i1 %cmp, double %z, double %y
- ret double %z.y
-}
-
-; CHECK-LABEL: default2:
-define double @default2(double %a, double %y, double %z) {
-; SAFE-NOT: fsel
-; UNSAFE: fsel
- %cmp = fcmp ult double %a, 0.000000e+00
- %z.y = select i1 %cmp, double %z, double %y
- ret double %z.y
-}
-
-attributes #0 = { "no-infs-fp-math"="false" }
-attributes #1 = { "no-nans-fp-math"="false" }
-
-attributes #2 = { "no-infs-fp-math"="false" }
-attributes #3 = { "no-infs-fp-math"="true" }
diff --git a/llvm/test/CodeGen/PowerPC/fsel.ll b/llvm/test/CodeGen/PowerPC/fsel.ll
index dea442d8404e1..c60bd4f32d663 100644
--- a/llvm/test/CodeGen/PowerPC/fsel.ll
+++ b/llvm/test/CodeGen/PowerPC/fsel.ll
@@ -1,6 +1,5 @@
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s
-; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-no-infs-fp-math -enable-no-nans-fp-math -mattr=-vsx | FileCheck -check-prefix=CHECK-FM %s
-; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-no-infs-fp-math -enable-no-nans-fp-math -mattr=+vsx | FileCheck -check-prefix=CHECK-FM-VSX %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-no-nans-fp-math -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
@@ -13,14 +12,21 @@ entry:
; CHECK: @zerocmp1
; CHECK-NOT: fsel
; CHECK: blr
+}
+
+define double @zerocmp1_finite(double %a, double %y, double %z) #0 {
+entry:
+ %cmp = fcmp ninf nnan ult double %a, 0.000000e+00
+ %z.y = select i1 %cmp, double %z, double %y
+ ret double %z.y
-; CHECK-FM: @zerocmp1
-; CHECK-FM: fsel 1, 1, 2, 3
-; CHECK-FM: blr
+; CHECK: @zerocmp1_finite
+; CHECK: fsel 1, 1, 2, 3
+; CHECK: blr
-; CHECK-FM-VSX: @zerocmp1
-; CHECK-FM-VSX: fsel 1, 1, 2, 3
-; CHECK-FM-VSX: blr
+; CHECK-VSX: @zerocmp1_finite
+; CHECK-VSX: fsel 1, 1, 2, 3
+; CHECK-VSX: blr
}
define double @zerocmp2(double %a, double %y, double %z) #0 {
@@ -32,16 +38,23 @@ entry:
; CHECK: @zerocmp2
; CHECK-NOT: fsel
; CHECK: blr
+}
+
+define double @zerocmp2_finite(double %a, double %y, double %z) #0 {
+entry:
+ %cmp = fcmp ninf nnan ogt double %a, 0.000000e+00
+ %y.z = select i1 %cmp, double %y, double %z
+ ret double %y.z
-; CHECK-FM: @zerocmp2
-; CHECK-FM: fneg [[REG:[0-9]+]], 1
-; CHECK-FM: fsel 1, [[REG]], 3, 2
-; CHECK-FM: blr
+; CHECK: @zerocmp2_finite
+; CHECK: fneg [[REG:[0-9]+]], 1
+; CHECK: fsel 1, [[REG]], 3, 2
+; CHECK: blr
-; CHECK-FM-VSX: @zerocmp2
-; CHECK-FM-VSX: xsnegdp [[REG:[0-9]+]], 1
-; CHECK-FM-VSX: fsel 1, [[REG]], 3, 2
-; CHECK-FM-VSX: blr
+; CHECK-VSX: @zerocmp2_finite
+; CHECK-VSX: xsnegdp [[REG:[0-9]+]], 1
+; CHECK-VSX: fsel 1, [[REG]], 3, 2
+; CHECK-VSX: blr
}
define double @zerocmp3(double %a, double %y, double %z) #0 {
@@ -53,18 +66,25 @@ entry:
; CHECK: @zerocmp3
; CHECK-NOT: fsel
; CHECK: blr
+}
+
+define double @zerocmp3_finite(double %a, double %y, double %z) #0 {
+entry:
+ %cmp = fcmp ninf nnan oeq double %a, 0.000000e+00
+ %y.z = select i1 %cmp, double %y, double %z
+ ret double %y.z
-; CHECK-FM: @zerocmp3
-; CHECK-FM: fsel [[REG:[0-9]+]], 1, 2, 3
-; CHECK-FM: fneg [[REG2:[0-9]+]], 1
-; CHECK-FM: fsel 1, [[REG2]], [[REG]], 3
-; CHECK-FM: blr
+; CHECK: @zerocmp3_finite
+; CHECK: fsel [[REG:[0-9]+]], 1, 2, 3
+; CHECK: fneg [[REG2:[0-9]+]], 1
+; CHECK: fsel 1, [[REG2]], [[REG]], 3
+; CHECK: blr
-; CHECK-FM-VSX: @zerocmp3
-; CHECK-FM-VSX: fsel [[REG:[0-9]+]], 1, 2, 3
-; CHECK-FM-VSX: xsnegdp [[REG2:[0-9]+]], 1
-; CHECK-FM-VSX: fsel 1, [[REG2]], [[REG]], 3
-; CHECK-FM-VSX: blr
+; CHECK-VSX: @zerocmp3_finite
+; CHECK-VSX: fsel [[REG:[0-9]+]], 1, 2, 3
+; CHECK-VSX: xsnegdp [[REG2:[0-9]+]], 1
+; CHECK-VSX: fsel 1, [[REG2]], [[REG]], 3
+; CHECK-VSX: blr
}
define double @min1(double %a, double %b) #0 {
@@ -76,16 +96,23 @@ entry:
; CHECK: @min1
; CHECK-NOT: fsel
; CHECK: blr
+}
+
+define double @min1_finite(double %a, double %b) #0 {
+entry:
+ %cmp = fcmp ninf nnan ole double %a, %b
+ %cond = select i1 %cmp, double %a, double %b
+ ret double %cond
-; CHECK-FM: @min1
-; CHECK-FM: fsub [[REG:[0-9]+]], 2, 1
-; CHECK-FM: fsel 1, [[REG]], 1, 2
-; CHECK-FM: blr
+; CHECK: @min1_finite
+; CHECK: fsub [[REG:[0-9]+]], 2, 1
+; CHECK: fsel 1, [[REG]], 1, 2
+; CHECK: blr
-; CHECK-FM-VSX: @min1
-; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 2, 1
-; CHECK-FM-VSX: fsel 1, [[REG]], 1, 2
-; CHECK-FM-VSX: blr
+; CHECK-VSX: @min1_finite
+; CHECK-VSX: xssubdp [[REG:[0-9]+]], 2, 1
+; CHECK-VSX: fsel 1, [[REG]], 1, 2
+; CHECK-VSX: blr
}
define double @max1(double %a, double %b) #0 {
@@ -97,16 +124,23 @@ entry:
; CHECK: @max1
; CHECK-NOT: fsel
; CHECK: blr
+}
+
+define double @max1_finite(double %a, double %b) #0 {
+entry:
+ %cmp = fcmp ninf nnan oge double %a, %b
+ %cond = select i1 %cmp, double %a, double %b
+ ret double %cond
-; CHECK-FM: @max1
-; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2
-; CHECK-FM: fsel 1, [[REG]], 1, 2
-; CHECK-FM: blr
+; CHECK: @max1_finite
+; CHECK: fsub [[REG:[0-9]+]], 1, 2
+; CHECK: fsel 1, [[REG]], 1, 2
+; CHECK: blr
-; CHECK-FM-VSX: @max1
-; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 1, 2
-; CHECK-FM-VSX: fsel 1, [[REG]], 1, 2
-; CHECK-FM-VSX: blr
+; CHECK-VSX: @max1_finite
+; CHECK-VSX: xssubdp [[REG:[0-9]+]], 1, 2
+; CHECK-VSX: fsel 1, [[REG]], 1, 2
+; CHECK-VSX: blr
}
define double @cmp1(double %a, double %b, double %y, double %z) #0 {
@@ -118,16 +152,23 @@ entry:
; CHECK: @cmp1
; CHECK-NOT: fsel
; CHECK: blr
+}
+
+define double @cmp1_finite(double %a, double %b, double %y, double %z) #0 {
+entry:
+ %cmp = fcmp ninf nnan ult double %a, %b
+ %z.y = select i1 %cmp, double %z, double %y
+ ret double %z.y
-; CHECK-FM: @cmp1
-; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2
-; CHECK-FM: fsel 1, [[REG]], 3, 4
-; CHECK-FM: blr
+; CHECK: @cmp1_finite
+; CHECK: fsub [[REG:[0-9]+]], 1, 2
+; CHECK: fsel 1, [[REG]], 3, 4
+; CHECK: blr
-; CHECK-FM-VSX: @cmp1
-; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 1, 2
-; CHECK-FM-VSX: fsel 1, [[REG]], 3, 4
-; CHECK-FM-VSX: blr
+; CHECK-VSX: @cmp1_finite
+; CHECK-VSX: xssubdp [[REG:[0-9]+]], 1, 2
+; CHECK-VSX: fsel 1, [[REG]], 3, 4
+; CHECK-VSX: blr
}
define double @cmp2(double %a, double %b, double %y, double %z) #0 {
@@ -139,16 +180,23 @@ entry:
; CHECK: @cmp2
; CHECK-NOT: fsel
; CHECK: blr
+}
+
+define double @cmp2_finite(double %a, double %b, double %y, double %z) #0 {
+entry:
+ %cmp = fcmp ninf nnan ogt double %a, %b
+ %y.z = select i1 %cmp, double %y, double %z
+ ret double %y.z
-; CHECK-FM: @cmp2
-; CHECK-FM: fsub [[REG:[0-9]+]], 2, 1
-; CHECK-FM: fsel 1, [[REG]], 4, 3
-; CHECK-FM: blr
+; CHECK: @cmp2_finite
+; CHECK: fsub [[REG:[0-9]+]], 2, 1
+; CHECK: fsel 1, [[REG]], 4, 3
+; CHECK: blr
-; CHECK-FM-VSX: @cmp2
-; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 2, 1
-; CHECK-FM-VSX: fsel 1, [[REG]], 4, 3
-; CHECK-FM-VSX: blr
+; CHECK-VSX: @cmp2_finite
+; CHECK-VSX: xssubdp [[REG:[0-9]+]], 2, 1
+; CHECK-VSX: fsel 1, [[REG]], 4, 3
+; CHECK-VSX: blr
}
define double @cmp3(double %a, double %b, double %y, double %z) #0 {
@@ -160,20 +208,27 @@ entry:
; CHECK: @cmp3
; CHECK-NOT: fsel
; CHECK: blr
+}
+
+define double @cmp3_finite(double %a, double %b, double %y, double %z) #0 {
+entry:
+ %cmp = fcmp ninf nnan oeq double %a, %b
+ %y.z = select i1 %cmp, double %y, double %z
+ ret double %y.z
-; CHECK-FM: @cmp3
-; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2
-; CHECK-FM: fsel [[REG2:[0-9]+]], [[REG]], 3, 4
-; CHECK-FM: fneg [[REG3:[0-9]+]], [[REG]]
-; CHECK-FM: fsel 1, [[REG3]], [[REG2]], 4
-; CHECK-FM: blr
+; CHECK: @cmp3_finite
+; CHECK: fsub [[REG:[0-9]+]], 1, 2
+; CHECK: fsel [[REG2:[0-9]+]], [[REG]], 3, 4
+; CHECK: fneg [[REG3:[0-9]+]], [[REG]]
+; CHECK: fsel 1, [[REG3]], [[REG2]], 4
+; CHECK: blr
-; CHECK-FM-VSX: @cmp3
-; CHECK-FM-VSX: xssubdp [[REG:[0-9]+]], 1, 2
-; CHECK-FM-VSX: fsel [[REG2:[0-9]+]], [[REG]], 3, 4
-; CHECK-FM-VSX: xsnegdp [[REG3:[0-9]+]], [[REG]]
-; CHECK-FM-VSX: fsel 1, [[REG3]], [[REG2]], 4
-; CHECK-FM-VSX: blr
+; CHECK-VSX: @cmp3_finite
+; CHECK-VSX: xssubdp [[REG:[0-9]+]], 1, 2
+; CHECK-VSX: fsel [[REG2:[0-9]+]], [[REG]], 3, 4
+; CHECK-VSX: xsnegdp [[REG3:[0-9]+]], [[REG]]
+; CHECK-VSX: fsel 1, [[REG3]], [[REG2]], 4
+; CHECK-VSX: blr
}
attributes #0 = { nounwind readnone }
diff --git a/llvm/test/CodeGen/PowerPC/scalar-equal.ll b/llvm/test/CodeGen/PowerPC/scalar-equal.ll
index 1832475e7795b..de829b5d54dee 100644
--- a/llvm/test/CodeGen/PowerPC/scalar-equal.ll
+++ b/llvm/test/CodeGen/PowerPC/scalar-equal.ll
@@ -1,57 +1,31 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names --enable-unsafe-fp-math \
-; RUN: -verify-machineinstrs --enable-no-signed-zeros-fp-math \
-; RUN: --enable-no-nans-fp-math --enable-no-infs-fp-math \
-; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
-; RUN: --check-prefix=FAST-P8
-; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names --enable-unsafe-fp-math \
-; RUN: -verify-machineinstrs --enable-no-signed-zeros-fp-math \
-; RUN: --enable-no-nans-fp-math --enable-no-infs-fp-math \
-; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
-; RUN: --check-prefix=FAST-P9
; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -verify-machineinstrs \
; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
-; RUN: --check-prefix=NO-FAST-P9
+; RUN: --check-prefix=P9
; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -verify-machineinstrs \
; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
-; RUN: --check-prefix=NO-FAST-P8
+; RUN: --check-prefix=P8
define double @testoeq(double %a, double %b, double %c, double %d) {
-; FAST-P8-LABEL: testoeq:
-; FAST-P8: # %bb.0: # %entry
-; FAST-P8-NEXT: xssubdp f0, f1, f2
-; FAST-P8-NEXT: fsel f1, f0, f3, f4
-; FAST-P8-NEXT: xsnegdp f0, f0
-; FAST-P8-NEXT: fsel f1, f0, f1, f4
-; FAST-P8-NEXT: blr
-;
-; FAST-P9-LABEL: testoeq:
-; FAST-P9: # %bb.0: # %entry
-; FAST-P9-NEXT: xssubdp f0, f1, f2
-; FAST-P9-NEXT: fsel f1, f0, f3, f4
-; FAST-P9-NEXT: xsnegdp f0, f0
-; FAST-P9-NEXT: fsel f1, f0, f1, f4
-; FAST-P9-NEXT: blr
+; P9-LABEL: testoeq:
+; P9: # %bb.0: # %entry
+; P9-NEXT: xscmpudp cr0, f1, f2
+; P9-NEXT: beq cr0, .LBB0_2
+; P9-NEXT: # %bb.1: # %entry
+; P9-NEXT: fmr f3, f4
+; P9-NEXT: .LBB0_2: # %entry
+; P9-NEXT: fmr f1, f3
+; P9-NEXT: blr
;
-; NO-FAST-P9-LABEL: testoeq:
-; NO-FAST-P9: # %bb.0: # %entry
-; NO-FAST-P9-NEXT: xscmpudp cr0, f1, f2
-; NO-FAST-P9-NEXT: beq cr0, .LBB0_2
-; NO-FAST-P9-NEXT: # %bb.1: # %entry
-; NO-FAST-P9-NEXT: fmr f3, f4
-; NO-FAST-P9-NEXT: .LBB0_2: # %entry
-; NO-FAST-P9-NEXT: fmr f1, f3
-; NO-FAST-P9-NEXT: blr
-;
-; NO-FAST-P8-LABEL: testoeq:
-; NO-FAST-P8: # %bb.0: # %entry
-; NO-FAST-P8-NEXT: xscmpudp cr0, f1, f2
-; NO-FAST-P8-NEXT: beq cr0, .LBB0_2
-; NO-FAST-P8-NEXT: # %bb.1: # %entry
-; NO-FAST-P8-NEXT: fmr f3, f4
-; NO-FAST-P8-NEXT: .LBB0_2: # %entry
-; NO-FAST-P8-NEXT: fmr f1, f3
-; NO-FAST-P8-NEXT: blr
+; P8-LABEL: testoeq:
+; P8: # %bb.0: # %entry
+; P8-NEXT: xscmpudp cr0, f1, f2
+; P8-NEXT: beq cr0, .LBB0_2
+; P8-NEXT: # %bb.1: # %entry
+; P8-NEXT: fmr f3, f4
+; P8-NEXT: .LBB0_2: # %entry
+; P8-NEXT: fmr f1, f3
+; P8-NEXT: blr
entry:
%cmp = fcmp oeq double %a, %b
%cond = select i1 %cmp, double %c, double %d
@@ -59,37 +33,21 @@ entry:
}
define double @testoeq_fast(double %a, double %b, double %c, double %d) {
-; FAST-P8-LABEL: testoeq_fast:
-; FAST-P8: # %bb.0: # %entry
-; FAST-P8-NEXT: xssubdp f0, f1, f2
-; FAST-P8-NEXT: fsel f1, f0, f3, f4
-; FAST-P8-NEXT: xsnegdp f0, f0
-; FAST-P8-NEXT: fsel f1, f0, f1, f4
-; FAST-P8-NEXT: blr
-;
-; FAST-P9-LABEL: testoeq_fast:
-; FAST-P9: # %bb.0: # %entry
-; FAST-P9-NEXT: xssubdp f0, f1, f2
-; FAST-P9-NEXT: fsel f1, f0, f3, f4
-; FAST-P9-NEXT: xsnegdp f0, f0
-; FAST-P9-NEXT: fsel f1, f0, f1, f4
-; FAST-P9-NEXT: blr
-;
-; NO-FAST-P9-LABEL: testoeq_fast:
-; NO-FAST-P9: # %bb.0: # %entry
-; NO-FAST-P9-NEXT: xssubdp f0, f1, f2
-; NO-FAST-P9-NEXT: fsel f1, f0, f3, f4
-; NO-FAST-P9-NEXT: xsnegdp f0, f0
-; NO-FAST-P9-NEXT: fsel f1, f0, f1, f4
-; NO-FAST-P9-NEXT: blr
+; P9-LABEL: testoeq_fast:
+; P9: # %bb.0: # %entry
+; P9-NEXT: xssubdp f0, f1, f2
+; P9-NEXT: fsel f1, f0, f3, f4
+; P9-NEXT: xsnegdp f0, f0
+; P9-NEXT: fsel f1, f0, f1, f4
+; P9-NEXT: blr
;
-; NO-FAST-P8-LABEL: testoeq_fast:
-; NO-FAST-P8: # %bb.0: # %entry
-; NO-FAST-P8-NEXT: xssubdp f0, f1, f2
-; NO-FAST-P8-NEXT: fsel f1, f0, f3, f4
-; NO-FAST-P8-NEXT: xsnegdp f0, f0
-; NO-FAST-P8-NEXT: fsel f1, f0, f1, f4
-; NO-FAST-P8-NEXT: blr
+; P8-LABEL: testoeq_fast:
+; P8: # %bb.0: # %entry
+; P8-NEXT: xssubdp f0, f1, f2
+; P8-NEXT: fsel f1, f0, f3, f4
+; P8-NEXT: xsnegdp f0, f0
+; P8-NEXT: fsel f1, f0, f1, f4
+; P8-NEXT: blr
entry:
%cmp = fcmp nnan ninf nsz oeq double %a, %b
%cond = select nnan ninf nsz i1 %cmp, double %c, double %d
More information about the llvm-commits
mailing list