[llvm] 2914642 - [AMDGPU] NFC: Add Opcode variants for TII->isMFMA* (#163874)

via llvm-commits llvm-commits at lists.llvm.org
Thu Oct 16 16:59:39 PDT 2025


Author: Jeffrey Byrnes
Date: 2025-10-16T16:59:35-07:00
New Revision: 29146423b8dde6bbe8ae709973271536067add24

URL: https://github.com/llvm/llvm-project/commit/29146423b8dde6bbe8ae709973271536067add24
DIFF: https://github.com/llvm/llvm-project/commit/29146423b8dde6bbe8ae709973271536067add24.diff

LOG: [AMDGPU] NFC: Add Opcode variants for TII->isMFMA* (#163874)

Adds a couple missing variants based on opcode.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIInstrInfo.h

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index e979eeb0bdf3a..df27ec1f8de8c 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -879,6 +879,11 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
            MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64;
   }
 
+  bool isMFMA(uint16_t Opcode) const {
+    return isMAI(Opcode) && Opcode != AMDGPU::V_ACCVGPR_WRITE_B32_e64 &&
+           Opcode != AMDGPU::V_ACCVGPR_READ_B32_e64;
+  }
+
   static bool isDOT(const MachineInstr &MI) {
     return MI.getDesc().TSFlags & SIInstrFlags::IsDOT;
   }
@@ -895,6 +900,10 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
     return isMFMA(MI) || isWMMA(MI) || isSWMMAC(MI);
   }
 
+  bool isMFMAorWMMA(uint16_t Opcode) const {
+    return isMFMA(Opcode) || isWMMA(Opcode) || isSWMMAC(Opcode);
+  }
+
   static bool isSWMMAC(const MachineInstr &MI) {
     return MI.getDesc().TSFlags & SIInstrFlags::IsSWMMAC;
   }


        


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