[llvm] [WebAssembly] Add pattern for relaxed laneselect (from bitselect simd) (PR #163807)
Jasmine Tang via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 16 08:42:15 PDT 2025
https://github.com/badumbatish created https://github.com/llvm/llvm-project/pull/163807
Related to #55932
>From 96158b7394bc247c73d0a631563ab62aa19b250b Mon Sep 17 00:00:00 2001
From: Jasmine Tang <jjasmine at igalia.com>
Date: Thu, 16 Oct 2025 08:28:35 -0700
Subject: [PATCH 1/2] precommit
---
.../WebAssembly/simd-relaxed-laneselect.ll | 79 +++++++++++++++++++
1 file changed, 79 insertions(+)
create mode 100644 llvm/test/CodeGen/WebAssembly/simd-relaxed-laneselect.ll
diff --git a/llvm/test/CodeGen/WebAssembly/simd-relaxed-laneselect.ll b/llvm/test/CodeGen/WebAssembly/simd-relaxed-laneselect.ll
new file mode 100644
index 0000000000000..048f5029b136d
--- /dev/null
+++ b/llvm/test/CodeGen/WebAssembly/simd-relaxed-laneselect.ll
@@ -0,0 +1,79 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+; RUN: llc < %s -verify-machineinstrs -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128,+relaxed-simd | FileCheck %s --check-prefix=RELAXED
+; RUN: llc < %s -verify-machineinstrs -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s --check-prefix=SIMD
+
+; Test that bitselect intrinsic lowers to relaxed_laneselect when relaxed-simd is enabled
+
+target triple = "wasm32-unknown-unknown"
+
+define <16 x i8> @bitselect_to_laneselect_v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
+; RELAXED-LABEL: bitselect_to_laneselect_v16i8:
+; RELAXED: .functype bitselect_to_laneselect_v16i8 (v128, v128, v128) -> (v128)
+; RELAXED-NEXT: # %bb.0:
+; RELAXED-NEXT: v128.bitselect $push0=, $0, $1, $2
+; RELAXED-NEXT: # fallthrough-return
+;
+; SIMD-LABEL: bitselect_to_laneselect_v16i8:
+; SIMD: .functype bitselect_to_laneselect_v16i8 (v128, v128, v128) -> (v128)
+; SIMD-NEXT: # %bb.0:
+; SIMD-NEXT: v128.bitselect $push0=, $0, $1, $2
+; SIMD-NEXT: # fallthrough-return
+ %res = call <16 x i8> @llvm.wasm.bitselect.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c)
+ ret <16 x i8> %res
+}
+
+define <8 x i16> @bitselect_to_laneselect_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) {
+; RELAXED-LABEL: bitselect_to_laneselect_v8i16:
+; RELAXED: .functype bitselect_to_laneselect_v8i16 (v128, v128, v128) -> (v128)
+; RELAXED-NEXT: # %bb.0:
+; RELAXED-NEXT: v128.bitselect $push0=, $0, $1, $2
+; RELAXED-NEXT: # fallthrough-return
+;
+; SIMD-LABEL: bitselect_to_laneselect_v8i16:
+; SIMD: .functype bitselect_to_laneselect_v8i16 (v128, v128, v128) -> (v128)
+; SIMD-NEXT: # %bb.0:
+; SIMD-NEXT: v128.bitselect $push0=, $0, $1, $2
+; SIMD-NEXT: # fallthrough-return
+ %res = call <8 x i16> @llvm.wasm.bitselect.v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c)
+ ret <8 x i16> %res
+}
+
+define <4 x i32> @bitselect_to_laneselect_v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
+; RELAXED-LABEL: bitselect_to_laneselect_v4i32:
+; RELAXED: .functype bitselect_to_laneselect_v4i32 (v128, v128, v128) -> (v128)
+; RELAXED-NEXT: # %bb.0:
+; RELAXED-NEXT: v128.bitselect $push0=, $0, $1, $2
+; RELAXED-NEXT: # fallthrough-return
+;
+; SIMD-LABEL: bitselect_to_laneselect_v4i32:
+; SIMD: .functype bitselect_to_laneselect_v4i32 (v128, v128, v128) -> (v128)
+; SIMD-NEXT: # %bb.0:
+; SIMD-NEXT: v128.bitselect $push0=, $0, $1, $2
+; SIMD-NEXT: # fallthrough-return
+ %res = call <4 x i32> @llvm.wasm.bitselect.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c)
+ ret <4 x i32> %res
+}
+
+define <2 x i64> @bitselect_to_laneselect_v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
+; RELAXED-LABEL: bitselect_to_laneselect_v2i64:
+; RELAXED: .functype bitselect_to_laneselect_v2i64 (v128, v128, v128) -> (v128)
+; RELAXED-NEXT: # %bb.0:
+; RELAXED-NEXT: v128.bitselect $push0=, $0, $1, $2
+; RELAXED-NEXT: # fallthrough-return
+;
+; SIMD-LABEL: bitselect_to_laneselect_v2i64:
+; SIMD: .functype bitselect_to_laneselect_v2i64 (v128, v128, v128) -> (v128)
+; SIMD-NEXT: # %bb.0:
+; SIMD-NEXT: v128.bitselect $push0=, $0, $1, $2
+; SIMD-NEXT: # fallthrough-return
+ %res = call <2 x i64> @llvm.wasm.bitselect.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c)
+ ret <2 x i64> %res
+}
+
+
+
+declare <16 x i8> @llvm.wasm.bitselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
+declare <8 x i16> @llvm.wasm.bitselect.v8i16(<8 x i16>, <8 x i16>, <8 x i16>)
+declare <4 x i32> @llvm.wasm.bitselect.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
+declare <2 x i64> @llvm.wasm.bitselect.v2i64(<2 x i64>, <2 x i64>, <2 x i64>)
>From 9529e74baee6053cbe9d5b29b8919c78f1f8391b Mon Sep 17 00:00:00 2001
From: Jasmine Tang <jjasmine at igalia.com>
Date: Thu, 16 Oct 2025 08:28:49 -0700
Subject: [PATCH 2/2] Add pattern for laneselect
---
llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td | 7 +++++++
llvm/test/CodeGen/WebAssembly/simd-relaxed-laneselect.ll | 8 ++++----
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
index 49af78bce68c3..39f18b969d221 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -1662,6 +1662,13 @@ multiclass SIMDLANESELECT<Vec vec, bits<32> op> {
(vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))],
vec.prefix#".relaxed_laneselect\t$dst, $a, $b, $c",
vec.prefix#".relaxed_laneselect", op>;
+
+ let AddedComplexity = 1 in {
+ def : Pat<(vec.vt (int_wasm_bitselect
+ (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c))),
+ (!cast<Instruction>("LANESELECT_"#vec) V128:$a, V128:$b, V128:$c)>,
+ Requires<[HasRelaxedSIMD]>;
+ }
}
defm "" : SIMDLANESELECT<I8x16, 0x109>;
diff --git a/llvm/test/CodeGen/WebAssembly/simd-relaxed-laneselect.ll b/llvm/test/CodeGen/WebAssembly/simd-relaxed-laneselect.ll
index 048f5029b136d..b63e9e166b8d2 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-relaxed-laneselect.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-relaxed-laneselect.ll
@@ -11,7 +11,7 @@ define <16 x i8> @bitselect_to_laneselect_v16i8(<16 x i8> %a, <16 x i8> %b, <16
; RELAXED-LABEL: bitselect_to_laneselect_v16i8:
; RELAXED: .functype bitselect_to_laneselect_v16i8 (v128, v128, v128) -> (v128)
; RELAXED-NEXT: # %bb.0:
-; RELAXED-NEXT: v128.bitselect $push0=, $0, $1, $2
+; RELAXED-NEXT: i8x16.relaxed_laneselect $push0=, $0, $1, $2
; RELAXED-NEXT: # fallthrough-return
;
; SIMD-LABEL: bitselect_to_laneselect_v16i8:
@@ -27,7 +27,7 @@ define <8 x i16> @bitselect_to_laneselect_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x
; RELAXED-LABEL: bitselect_to_laneselect_v8i16:
; RELAXED: .functype bitselect_to_laneselect_v8i16 (v128, v128, v128) -> (v128)
; RELAXED-NEXT: # %bb.0:
-; RELAXED-NEXT: v128.bitselect $push0=, $0, $1, $2
+; RELAXED-NEXT: i16x8.relaxed_laneselect $push0=, $0, $1, $2
; RELAXED-NEXT: # fallthrough-return
;
; SIMD-LABEL: bitselect_to_laneselect_v8i16:
@@ -43,7 +43,7 @@ define <4 x i32> @bitselect_to_laneselect_v4i32(<4 x i32> %a, <4 x i32> %b, <4 x
; RELAXED-LABEL: bitselect_to_laneselect_v4i32:
; RELAXED: .functype bitselect_to_laneselect_v4i32 (v128, v128, v128) -> (v128)
; RELAXED-NEXT: # %bb.0:
-; RELAXED-NEXT: v128.bitselect $push0=, $0, $1, $2
+; RELAXED-NEXT: i32x4.relaxed_laneselect $push0=, $0, $1, $2
; RELAXED-NEXT: # fallthrough-return
;
; SIMD-LABEL: bitselect_to_laneselect_v4i32:
@@ -59,7 +59,7 @@ define <2 x i64> @bitselect_to_laneselect_v2i64(<2 x i64> %a, <2 x i64> %b, <2 x
; RELAXED-LABEL: bitselect_to_laneselect_v2i64:
; RELAXED: .functype bitselect_to_laneselect_v2i64 (v128, v128, v128) -> (v128)
; RELAXED-NEXT: # %bb.0:
-; RELAXED-NEXT: v128.bitselect $push0=, $0, $1, $2
+; RELAXED-NEXT: i64x2.relaxed_laneselect $push0=, $0, $1, $2
; RELAXED-NEXT: # fallthrough-return
;
; SIMD-LABEL: bitselect_to_laneselect_v2i64:
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