[llvm] [RISCV][llvm] Preliminary P extension codegen support (PR #162668)

[Craig Topper via llvm-commits]

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@@ -479,6 +490,24 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
       ISD::FTRUNC,       ISD::FRINT,         ISD::FROUND,
       ISD::FROUNDEVEN,   ISD::FCANONICALIZE};
 
+  if (Subtarget.hasStdExtP()) {
+    // load/store are already handled by pattern matching
+    SmallVector<MVT, 2> VTs = {MVT::v2i16, MVT::v4i8};
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topperc wrote:

> do we want v4i16 or v2i32?

If we go with v2i32, then loads need an extend to move bits [31:16] from memory to bits [47:32] of the register. Stores need to do the opposite. Not sure how easy that is to do in the P extension. I don't see any instructions that an extend an element. Maybe I missed it?

https://github.com/llvm/llvm-project/pull/162668