[llvm] [RISCV] Modify RegMask Settings of Scalar Library Functions to Reduce Spills (PR #163311)

[via llvm-commits]

Leilongjie2000 wrote:

Hi, Thanks for your reply!  I’d like to clarify that our change fully follows the calling convention.

First, CSR_ILP32D_LP64D_V_RegMask is based on CSR_ILP32D_LP64D_RegMask (scalar callee-saved registers) and only adds a subset of vector callee-saved registers (v1–v7, v24–v31), not all vector registers.

Second, all library functions comply with the ABI design and restore callee-saved registers upon exit — even scalar functions like memset and memcpy that internally use vector instructions.

Therefore, when the subtarget supports the V extension, making vector callee-saved registers available is  valid. Additionally, we verified correctness on SPEC CPU2006 and encountered no problems.

Happy to continue the discussion :)

> There's no guarantee in the ABI that scalar function doen't use vector registers. If glibc starts allowing vector code in memcpy, memset, it will be very easy for library code to break this.
> 
> Have you tried using a vector math library like [sleef](https://sleef.org/) that contains a vectorized version of expf for RISC-V?
> 
> Or have you tried modifying the cost model to not vectorize functions with scalar library calls? Is it profitable to vectorize if you have to keep extracting elements?


https://github.com/llvm/llvm-project/pull/163311