[llvm] [X86] Fix places where we use X86ISD::CMP where we should use SUBS (PR #163476)
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Tue Oct 14 17:04:00 PDT 2025
https://github.com/AZero13 updated https://github.com/llvm/llvm-project/pull/163476
>From 0828dd5e70a479c73ac7eabac30d1e1d1e413fcd Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Tue, 14 Oct 2025 20:00:30 -0400
Subject: [PATCH] [X86] Fix places where we use X86ISD::CMP where we should use
SUBS
CMP is meant for comparisons with 0.
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 37 +++++++++++++++++--------
1 file changed, 25 insertions(+), 12 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index c32b1a66356ea..25c4b7cb6223e 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -23117,9 +23117,11 @@ static SDValue LowerVectorAllEqual(const SDLoc &DL, SDValue LHS, SDValue RHS,
DAG.getNode(ISD::OR, DL, MVT::i32, Lo, Hi),
DAG.getConstant(0, DL, MVT::i32));
}
- return DAG.getNode(X86ISD::CMP, DL, MVT::i32,
- DAG.getBitcast(IntVT, MaskBits(LHS)),
- DAG.getBitcast(IntVT, MaskBits(RHS)));
+ SDVTList CmpVTs = DAG.getVTList(IntVT, MVT::i32);
+ return DAG
+ .getNode(X86ISD::SUB, DL, CmpVTs, DAG.getBitcast(IntVT, MaskBits(LHS)),
+ DAG.getBitcast(IntVT, MaskBits(RHS)))
+ .getValue(1);
}
// Without PTEST, a masked v2i64 or-reduction is not faster than
@@ -48966,9 +48968,12 @@ static SDValue combineSetCCMOVMSK(SDValue EFLAGS, X86::CondCode &CC,
DAG.ComputeNumSignBits(BC) > (BCNumEltBits - NumEltBits)) {
SDLoc DL(EFLAGS);
APInt CmpMask = APInt::getLowBitsSet(32, IsAnyOf ? 0 : BCNumElts);
- return DAG.getNode(X86ISD::CMP, DL, MVT::i32,
- DAG.getNode(X86ISD::MOVMSK, DL, MVT::i32, BC),
- DAG.getConstant(CmpMask, DL, MVT::i32));
+ SDVTList CmpVTs = DAG.getVTList(MVT::i32, MVT::i32);
+ return DAG
+ .getNode(X86ISD::SUB, DL, CmpVTs,
+ DAG.getNode(X86ISD::MOVMSK, DL, MVT::i32, BC),
+ DAG.getConstant(CmpMask, DL, MVT::i32))
+ .getValue(1);
}
}
@@ -48987,9 +48992,12 @@ static SDValue combineSetCCMOVMSK(SDValue EFLAGS, X86::CondCode &CC,
DAG.getBitcast(SubVT, Ops[0]),
DAG.getBitcast(SubVT, Ops[1]));
V = DAG.getBitcast(VecVT.getHalfNumVectorElementsVT(), V);
- return DAG.getNode(X86ISD::CMP, DL, MVT::i32,
- DAG.getNode(X86ISD::MOVMSK, DL, MVT::i32, V),
- DAG.getConstant(CmpMask, DL, MVT::i32));
+ SDVTList CmpVTs = DAG.getVTList(MVT::i32, MVT::i32);
+ return DAG
+ .getNode(X86ISD::SUB, DL, CmpVTs,
+ DAG.getNode(X86ISD::MOVMSK, DL, MVT::i32, V),
+ DAG.getConstant(CmpMask, DL, MVT::i32))
+ .getValue(1);
}
}
@@ -49072,8 +49080,11 @@ static SDValue combineSetCCMOVMSK(SDValue EFLAGS, X86::CondCode &CC,
Result = DAG.getNode(ISD::AND, DL, MVT::i32, Result,
DAG.getConstant(0xAAAAAAAA, DL, MVT::i32));
}
- return DAG.getNode(X86ISD::CMP, DL, MVT::i32, Result,
- DAG.getConstant(CmpMask, DL, MVT::i32));
+ SDVTList CmpVTs = DAG.getVTList(MVT::i32, MVT::i32);
+ return DAG
+ .getNode(X86ISD::SUB, DL, CmpVTs, Result,
+ DAG.getConstant(CmpMask, DL, MVT::i32))
+ .getValue(1);
}
}
}
@@ -49106,7 +49117,9 @@ static SDValue combineSetCCMOVMSK(SDValue EFLAGS, X86::CondCode &CC,
Result = DAG.getNode(X86ISD::MOVMSK, DL, MVT::i32, Result);
Result =
DAG.getZExtOrTrunc(Result, DL, EFLAGS.getOperand(0).getValueType());
- return DAG.getNode(X86ISD::CMP, DL, MVT::i32, Result, EFLAGS.getOperand(1));
+ SDVTList CmpVTs = DAG.getVTList(Result.getValueType(), MVT::i32);
+ return DAG.getNode(X86ISD::SUB, DL, CmpVTs, Result, EFLAGS.getOperand(1))
+ .getValue(1);
}
// MOVMSKPS(V) !=/== 0 -> TESTPS(V,V)
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