[llvm] [X86] Fix places where we use X86ISD::CMP where we should use SUBS (PR #163476)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-x86

Author: AZero13 (AZero13)

<details>
<summary>Changes</summary>

CMP is meant for comparisons with 0.

---
Full diff: https://github.com/llvm/llvm-project/pull/163476.diff


1 Files Affected:

- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+14-9) 


``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index c32b1a66356ea..eea60bf905fa9 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -23117,9 +23117,10 @@ static SDValue LowerVectorAllEqual(const SDLoc &DL, SDValue LHS, SDValue RHS,
                          DAG.getNode(ISD::OR, DL, MVT::i32, Lo, Hi),
                          DAG.getConstant(0, DL, MVT::i32));
     }
-    return DAG.getNode(X86ISD::CMP, DL, MVT::i32,
+    SDVTList CmpVTs = DAG.getVTList(IntVT, MVT::i32);
+    return DAG.getNode(X86ISD::SUB, DL, CmpVTs,
                        DAG.getBitcast(IntVT, MaskBits(LHS)),
-                       DAG.getBitcast(IntVT, MaskBits(RHS)));
+                       DAG.getBitcast(IntVT, MaskBits(RHS))).getValue(1);
   }
 
   // Without PTEST, a masked v2i64 or-reduction is not faster than
@@ -48966,9 +48967,10 @@ static SDValue combineSetCCMOVMSK(SDValue EFLAGS, X86::CondCode &CC,
         DAG.ComputeNumSignBits(BC) > (BCNumEltBits - NumEltBits)) {
       SDLoc DL(EFLAGS);
       APInt CmpMask = APInt::getLowBitsSet(32, IsAnyOf ? 0 : BCNumElts);
-      return DAG.getNode(X86ISD::CMP, DL, MVT::i32,
+      SDVTList CmpVTs = DAG.getVTList(MVT::i32, MVT::i32);
+      return DAG.getNode(X86ISD::SUB, DL, CmpVTs,
                          DAG.getNode(X86ISD::MOVMSK, DL, MVT::i32, BC),
-                         DAG.getConstant(CmpMask, DL, MVT::i32));
+                         DAG.getConstant(CmpMask, DL, MVT::i32)).getValue(1);
     }
   }
 
@@ -48987,9 +48989,10 @@ static SDValue combineSetCCMOVMSK(SDValue EFLAGS, X86::CondCode &CC,
                               DAG.getBitcast(SubVT, Ops[0]),
                               DAG.getBitcast(SubVT, Ops[1]));
       V = DAG.getBitcast(VecVT.getHalfNumVectorElementsVT(), V);
-      return DAG.getNode(X86ISD::CMP, DL, MVT::i32,
+      SDVTList CmpVTs = DAG.getVTList(MVT::i32, MVT::i32);
+      return DAG.getNode(X86ISD::SUB, DL, CmpVTs,
                          DAG.getNode(X86ISD::MOVMSK, DL, MVT::i32, V),
-                         DAG.getConstant(CmpMask, DL, MVT::i32));
+                         DAG.getConstant(CmpMask, DL, MVT::i32)).getValue(1);
     }
   }
 
@@ -49072,8 +49075,9 @@ static SDValue combineSetCCMOVMSK(SDValue EFLAGS, X86::CondCode &CC,
           Result = DAG.getNode(ISD::AND, DL, MVT::i32, Result,
                                DAG.getConstant(0xAAAAAAAA, DL, MVT::i32));
         }
-        return DAG.getNode(X86ISD::CMP, DL, MVT::i32, Result,
-                           DAG.getConstant(CmpMask, DL, MVT::i32));
+        SDVTList CmpVTs = DAG.getVTList(MVT::i32, MVT::i32);
+        return DAG.getNode(X86ISD::SUB, DL, CmpVTs, Result,
+                           DAG.getConstant(CmpMask, DL, MVT::i32)).getValue(1);
       }
     }
   }
@@ -49106,7 +49110,8 @@ static SDValue combineSetCCMOVMSK(SDValue EFLAGS, X86::CondCode &CC,
     Result = DAG.getNode(X86ISD::MOVMSK, DL, MVT::i32, Result);
     Result =
         DAG.getZExtOrTrunc(Result, DL, EFLAGS.getOperand(0).getValueType());
-    return DAG.getNode(X86ISD::CMP, DL, MVT::i32, Result, EFLAGS.getOperand(1));
+    SDVTList CmpVTs = DAG.getVTList(Result.getValueType(), MVT::i32);
+    return DAG.getNode(X86ISD::SUB, DL, CmpVTs, Result, EFLAGS.getOperand(1)).getValue(1);
   }
 
   // MOVMSKPS(V) !=/== 0 -> TESTPS(V,V)

``````````

</details>


https://github.com/llvm/llvm-project/pull/163476