[llvm] [AMDGPU] Allow folding of non-subregs through REG_SEQUENCE (PR #151033)

[Matt Arsenault via llvm-commits]

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@@ -726,7 +731,9 @@ bool SIFoldOperandsImpl::updateOperand(FoldCandidate &Fold) const {
 
   // Rework once the VS_16 register class is updated to include proper
   // 16-bit SGPRs instead of 32-bit ones.
-  if (Old.getSubReg() == AMDGPU::lo16 && TRI->isSGPRReg(*MRI, New->getReg()))
+  if ((Old.getSubReg() == AMDGPU::lo16 &&
+       TRI->isSGPRReg(*MRI, New->getReg())) ||
+      !New->getSubReg())
     Old.setSubReg(AMDGPU::NoSubRegister);
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arsenm wrote:

I'm confused about the state of this hack. There are no 16-bit SGPRs, which is the problem. But sometimes there are, artificially? 

https://github.com/llvm/llvm-project/pull/151033