[llvm] [AMDGPU] Allow folding of non-subregs through REG_SEQUENCE (PR #151033)

[Matt Arsenault via llvm-commits]

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@@ -1465,6 +1477,33 @@ void SIFoldOperandsImpl::foldOperand(
       return;
   }
 
+  if (!FoldingImmLike && OpToFold.isReg() && ST->needsAlignedVGPRs()) {
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arsenm wrote:

This would be a separate PR, since it's not really related to this.

Adding an even aligned 32-bit register class would be difficult. It would be easier to model this as a 64-bit operand, and continue doing the pad-with-undef it does today. The issue is the hardware treats this like a 64-bit value anyway, so we can model it as a 64-bit input.

It would require doing something like:

```

def GWS_SpecialCaseRC : RegClassByHwMode<
    [DefaultMode, AVAlign2LoadStoreMode, AlignedVGPRNoAGPRMode],
    [VGPR_32, VReg_64_Align2, VReg_64_Align2]>, SIRegisterClassLike<32, true, true>;

```

And using that instead of VGPR_32 for the special case operands in the GWS instruction definitions. Then we'd need separate patterns for the FeatureRequiresAlignedVGPRs and !FeatureRequiresAlignedVGPRs cases 





https://github.com/llvm/llvm-project/pull/151033