[llvm] [RISCV] Enable (non trivial) remat for most scalar instructions (PR #162311)

[Craig Topper via llvm-commits]

================
@@ -3758,64 +3772,68 @@ define void @lshr_32bytes(ptr %src.ptr, ptr %byteOff.ptr, ptr %dst) nounwind {
 ; RV32I-NEXT:    lw s11, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 64
 ; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB12_190:
-; RV32I-NEXT:    mv a4, t3
-; RV32I-NEXT:    li t3, 0
-; RV32I-NEXT:    beq t1, t4, .LBB12_174
 ; RV32I-NEXT:  .LBB12_191:
-; RV32I-NEXT:    mv t3, a4
-; RV32I-NEXT:    li a4, 0
-; RV32I-NEXT:    beq t1, s4, .LBB12_175
+; RV32I-NEXT:    mv t5, t3
+; RV32I-NEXT:    li t3, 0
+; RV32I-NEXT:    beq t1, s11, .LBB12_174
 ; RV32I-NEXT:  .LBB12_192:
-; RV32I-NEXT:    mv a4, t3
+; RV32I-NEXT:    mv t3, t5
+; RV32I-NEXT:    li t5, 0
+; RV32I-NEXT:    beq t1, t6, .LBB12_175
+; RV32I-NEXT:  .LBB12_193:
+; RV32I-NEXT:    mv t5, t3
 ; RV32I-NEXT:    li t3, 0
 ; RV32I-NEXT:    beq t1, s9, .LBB12_176
-; RV32I-NEXT:  .LBB12_193:
-; RV32I-NEXT:    mv t3, a4
-; RV32I-NEXT:    li a4, 0
-; RV32I-NEXT:    beq t1, s2, .LBB12_177
 ; RV32I-NEXT:  .LBB12_194:
-; RV32I-NEXT:    mv a4, t3
-; RV32I-NEXT:    li t3, 0
-; RV32I-NEXT:    beq t1, s3, .LBB12_178
+; RV32I-NEXT:    mv t3, t5
+; RV32I-NEXT:    li t5, 0
+; RV32I-NEXT:    beq t1, s1, .LBB12_177
 ; RV32I-NEXT:  .LBB12_195:
-; RV32I-NEXT:    mv t3, a4
-; RV32I-NEXT:    beqz a7, .LBB12_179
+; RV32I-NEXT:    mv t5, t3
+; RV32I-NEXT:    li t3, 0
+; RV32I-NEXT:    beq t1, s2, .LBB12_178
 ; RV32I-NEXT:  .LBB12_196:
-; RV32I-NEXT:    mv a0, t3
-; RV32I-NEXT:    beqz t1, .LBB12_180
+; RV32I-NEXT:    mv t3, t5
+; RV32I-NEXT:    li t5, 0
+; RV32I-NEXT:    beq t1, s3, .LBB12_179
 ; RV32I-NEXT:  .LBB12_197:
-; RV32I-NEXT:    li s1, 0
-; RV32I-NEXT:    li a4, 0
-; RV32I-NEXT:    beq t1, s0, .LBB12_181
+; RV32I-NEXT:    mv t5, t3
+; RV32I-NEXT:    beqz a7, .LBB12_180
 ; RV32I-NEXT:  .LBB12_198:
-; RV32I-NEXT:    mv a4, s1
-; RV32I-NEXT:    li t3, 0
-; RV32I-NEXT:    beq t1, t6, .LBB12_182
+; RV32I-NEXT:    mv a0, t5
+; RV32I-NEXT:    beqz t1, .LBB12_181
 ; RV32I-NEXT:  .LBB12_199:
-; RV32I-NEXT:    mv t3, a4
-; RV32I-NEXT:    li a4, 0
-; RV32I-NEXT:    beq t1, t4, .LBB12_183
-; RV32I-NEXT:  .LBB12_200:
-; RV32I-NEXT:    mv a4, t3
+; RV32I-NEXT:    li s4, 0
 ; RV32I-NEXT:    li t3, 0
-; RV32I-NEXT:    beq t1, s4, .LBB12_184
+; RV32I-NEXT:    beq t1, s10, .LBB12_182
+; RV32I-NEXT:  .LBB12_200:
+; RV32I-NEXT:    mv t3, s4
+; RV32I-NEXT:    li t5, 0
+; RV32I-NEXT:    beq t1, s11, .LBB12_183
 ; RV32I-NEXT:  .LBB12_201:
-; RV32I-NEXT:    mv t3, a4
-; RV32I-NEXT:    li a4, 0
-; RV32I-NEXT:    beq t1, s9, .LBB12_185
-; RV32I-NEXT:  .LBB12_202:
-; RV32I-NEXT:    mv a4, t3
+; RV32I-NEXT:    mv t5, t3
 ; RV32I-NEXT:    li t3, 0
-; RV32I-NEXT:    beq t1, s2, .LBB12_186
+; RV32I-NEXT:    beq t1, t6, .LBB12_184
+; RV32I-NEXT:  .LBB12_202:
+; RV32I-NEXT:    mv t3, t5
+; RV32I-NEXT:    li t4, 0
+; RV32I-NEXT:    beq t1, s9, .LBB12_185
 ; RV32I-NEXT:  .LBB12_203:
-; RV32I-NEXT:    mv t3, a4
-; RV32I-NEXT:    li a4, 0
-; RV32I-NEXT:    beq t1, s3, .LBB12_187
+; RV32I-NEXT:    mv t4, t3
+; RV32I-NEXT:    li t3, 0
+; RV32I-NEXT:    beq t1, s1, .LBB12_186
 ; RV32I-NEXT:  .LBB12_204:
-; RV32I-NEXT:    mv a4, t3
-; RV32I-NEXT:    bnez a7, .LBB12_188
-; RV32I-NEXT:    j .LBB12_189
+; RV32I-NEXT:    mv t3, t4
+; RV32I-NEXT:    li t4, 0
+; RV32I-NEXT:    beq t1, s2, .LBB12_187
+; RV32I-NEXT:  .LBB12_205:
+; RV32I-NEXT:    mv t4, t3
+; RV32I-NEXT:    li t3, 0
+; RV32I-NEXT:    beq t1, s3, .LBB12_188
+; RV32I-NEXT:  .LBB12_206:
+; RV32I-NEXT:    mv t3, t4
+; RV32I-NEXT:    bnez a7, .LBB12_189
+; RV32I-NEXT:    j .LBB12_190
----------------
topperc wrote:

This code got quite a bit longer. Is it better?

https://github.com/llvm/llvm-project/pull/162311