[llvm] [RISCV] Enable (non trivial) remat for most scalar instructions (PR #162311)

[Craig Topper via llvm-commits]

================
@@ -4908,64 +4940,68 @@ define void @lshr_32bytes_wordOff(ptr %src.ptr, ptr %wordOff.ptr, ptr %dst) noun
 ; RV32I-NEXT:    lw s11, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 64
 ; RV32I-NEXT:    ret
-; RV32I-NEXT:  .LBB13_190:
-; RV32I-NEXT:    mv a4, t3
-; RV32I-NEXT:    li t3, 0
-; RV32I-NEXT:    beq t1, t4, .LBB13_174
 ; RV32I-NEXT:  .LBB13_191:
-; RV32I-NEXT:    mv t3, a4
-; RV32I-NEXT:    li a4, 0
-; RV32I-NEXT:    beq t1, s4, .LBB13_175
+; RV32I-NEXT:    mv t5, t3
+; RV32I-NEXT:    li t3, 0
+; RV32I-NEXT:    beq t1, s11, .LBB13_174
 ; RV32I-NEXT:  .LBB13_192:
-; RV32I-NEXT:    mv a4, t3
+; RV32I-NEXT:    mv t3, t5
+; RV32I-NEXT:    li t5, 0
+; RV32I-NEXT:    beq t1, t6, .LBB13_175
+; RV32I-NEXT:  .LBB13_193:
+; RV32I-NEXT:    mv t5, t3
 ; RV32I-NEXT:    li t3, 0
 ; RV32I-NEXT:    beq t1, s9, .LBB13_176
-; RV32I-NEXT:  .LBB13_193:
-; RV32I-NEXT:    mv t3, a4
-; RV32I-NEXT:    li a4, 0
-; RV32I-NEXT:    beq t1, s2, .LBB13_177
 ; RV32I-NEXT:  .LBB13_194:
-; RV32I-NEXT:    mv a4, t3
-; RV32I-NEXT:    li t3, 0
-; RV32I-NEXT:    beq t1, s3, .LBB13_178
+; RV32I-NEXT:    mv t3, t5
+; RV32I-NEXT:    li t5, 0
+; RV32I-NEXT:    beq t1, s1, .LBB13_177
 ; RV32I-NEXT:  .LBB13_195:
-; RV32I-NEXT:    mv t3, a4
-; RV32I-NEXT:    beqz a7, .LBB13_179
+; RV32I-NEXT:    mv t5, t3
+; RV32I-NEXT:    li t3, 0
+; RV32I-NEXT:    beq t1, s2, .LBB13_178
 ; RV32I-NEXT:  .LBB13_196:
-; RV32I-NEXT:    mv a0, t3
-; RV32I-NEXT:    beqz t1, .LBB13_180
+; RV32I-NEXT:    mv t3, t5
+; RV32I-NEXT:    li t5, 0
+; RV32I-NEXT:    beq t1, s3, .LBB13_179
 ; RV32I-NEXT:  .LBB13_197:
-; RV32I-NEXT:    li s1, 0
-; RV32I-NEXT:    li a4, 0
-; RV32I-NEXT:    beq t1, s0, .LBB13_181
+; RV32I-NEXT:    mv t5, t3
+; RV32I-NEXT:    beqz a7, .LBB13_180
 ; RV32I-NEXT:  .LBB13_198:
-; RV32I-NEXT:    mv a4, s1
-; RV32I-NEXT:    li t3, 0
-; RV32I-NEXT:    beq t1, t6, .LBB13_182
+; RV32I-NEXT:    mv a0, t5
+; RV32I-NEXT:    beqz t1, .LBB13_181
 ; RV32I-NEXT:  .LBB13_199:
-; RV32I-NEXT:    mv t3, a4
-; RV32I-NEXT:    li a4, 0
-; RV32I-NEXT:    beq t1, t4, .LBB13_183
-; RV32I-NEXT:  .LBB13_200:
-; RV32I-NEXT:    mv a4, t3
+; RV32I-NEXT:    li s4, 0
 ; RV32I-NEXT:    li t3, 0
-; RV32I-NEXT:    beq t1, s4, .LBB13_184
+; RV32I-NEXT:    beq t1, s10, .LBB13_182
+; RV32I-NEXT:  .LBB13_200:
+; RV32I-NEXT:    mv t3, s4
+; RV32I-NEXT:    li t5, 0
+; RV32I-NEXT:    beq t1, s11, .LBB13_183
 ; RV32I-NEXT:  .LBB13_201:
-; RV32I-NEXT:    mv t3, a4
-; RV32I-NEXT:    li a4, 0
-; RV32I-NEXT:    beq t1, s9, .LBB13_185
-; RV32I-NEXT:  .LBB13_202:
-; RV32I-NEXT:    mv a4, t3
+; RV32I-NEXT:    mv t5, t3
 ; RV32I-NEXT:    li t3, 0
-; RV32I-NEXT:    beq t1, s2, .LBB13_186
+; RV32I-NEXT:    beq t1, t6, .LBB13_184
+; RV32I-NEXT:  .LBB13_202:
+; RV32I-NEXT:    mv t3, t5
+; RV32I-NEXT:    li t4, 0
+; RV32I-NEXT:    beq t1, s9, .LBB13_185
 ; RV32I-NEXT:  .LBB13_203:
-; RV32I-NEXT:    mv t3, a4
-; RV32I-NEXT:    li a4, 0
-; RV32I-NEXT:    beq t1, s3, .LBB13_187
+; RV32I-NEXT:    mv t4, t3
+; RV32I-NEXT:    li t3, 0
+; RV32I-NEXT:    beq t1, s1, .LBB13_186
 ; RV32I-NEXT:  .LBB13_204:
-; RV32I-NEXT:    mv a4, t3
-; RV32I-NEXT:    bnez a7, .LBB13_188
-; RV32I-NEXT:    j .LBB13_189
+; RV32I-NEXT:    mv t3, t4
+; RV32I-NEXT:    li t4, 0
+; RV32I-NEXT:    beq t1, s2, .LBB13_187
+; RV32I-NEXT:  .LBB13_205:
+; RV32I-NEXT:    mv t4, t3
+; RV32I-NEXT:    li t3, 0
+; RV32I-NEXT:    beq t1, s3, .LBB13_188
+; RV32I-NEXT:  .LBB13_206:
+; RV32I-NEXT:    mv t3, t4
+; RV32I-NEXT:    bnez a7, .LBB13_189
+; RV32I-NEXT:    j .LBB13_190
----------------
topperc wrote:

Longer

https://github.com/llvm/llvm-project/pull/162311