[llvm] [AArch64][llvm] Reject assembler for invalid TLBIP instructions (PR #162090)

[Jonathan Thackray via llvm-commits]

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@@ -816,6 +816,27 @@ def : BTI<"jc", 0b110>;
 // TLBI (translation lookaside buffer invalidate) instruction options.
 //===----------------------------------------------------------------------===//
 
+class TLBImode<bit v> {
+   bit TLBI_and_TLBIP = v;
+}
+
+def TLBI_only      : TLBImode<0>;
+def TLBI_and_TLBIP : TLBImode<1>;
+
+class TLBIPEntry<string name, bits<3> op1, bits<4> crn, bits<4> crm,
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jthackray wrote:

Sadly not.

https://github.com/llvm/llvm-project/pull/162090