[llvm] [AMDGPU] Enable overwrite ALU bit in sched.barrier mask (PR #160782)

[Jan Patrick Lehr via llvm-commits]

jplehr wrote:

> I think that if we want to do this, we need to be consistent across all different masks. For example, why do we constrain for SALU if our mask has both SALU and ALU, but we don't constrain for VMEM_READ if we have both VMEM_READ and VMEM.

Excellent points. I agree that it should be handled consistently. If you are ok with the direction that this change is going, then I can go ahead and do the changes and clarifications in the documents.

> 
> Also, I'm not sure what the intended use case is here.

The intended use is coming from Triton where I think they want to set everything and then selectively unset certain bits, e.g., MFMA.

I think the overall expectation is: If you specify "everything" (ALU bit) but then want to selectively unset something, the latter should take precedence.

https://github.com/llvm/llvm-project/pull/160782