[llvm] [AMDGPU] Enable overwrite ALU bit in sched.barrier mask (PR #160782)

[Jeffrey Byrnes via llvm-commits]

jrbyrnes wrote:

I think that if we want to do this, we need to be consistent across all different masks. For example, why do we constrain for SALU if our mask has both SALU and ALU, but we don't constrain for VMEM_READ if we have both VMEM_READ and VMEM.

Also, I'm not sure what the intended use case is here.

Needs tests.

https://github.com/llvm/llvm-project/pull/160782