[llvm] [AMDGPU] Sink uniform buffer address offsets into soffset (PR #160939)

[Krzysztof Drewniak via llvm-commits]

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@@ -341,8 +338,23 @@ void AMDGPUDAGToDAGISel::PreprocessISelDAG() {
 
     switch (N->getOpcode()) {
     case ISD::BUILD_VECTOR:
-      // TODO: Match load d16 from shl (extload:i16), 16
-      MadeChange |= matchLoadD16FromBuildVector(N);
+      // D16 optimization requires subtarget support
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krzysz00 wrote:

If we _were_ doing this on the MIR, I'd note that we do [vgpr + add] separation in ISelLowering/InstructionLegalizer.

So if anything I'd expect this to be with the other instruction-selection machinery.

https://github.com/llvm/llvm-project/pull/160939