[llvm] [AMDGPU] Sink uniform buffer address offsets into soffset (PR #160939)

[Matt Arsenault via llvm-commits]

================
@@ -341,8 +338,23 @@ void AMDGPUDAGToDAGISel::PreprocessISelDAG() {
 
     switch (N->getOpcode()) {
     case ISD::BUILD_VECTOR:
-      // TODO: Match load d16 from shl (extload:i16), 16
-      MadeChange |= matchLoadD16FromBuildVector(N);
+      // D16 optimization requires subtarget support
----------------
arsenm wrote:

This is a weird place to put the optimization. This doesn't have the special generalized RMW property that the d16 loads do.

 Buffers don't just come out of nowhere, you could do this on the IR.

https://github.com/llvm/llvm-project/pull/160939