[llvm] [RISCV] Add commutative support for Qualcomm uC Xqcicm extension (PR #160653)

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github-actions[bot] wrote:

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index df2b6ad01..f89c43ea3 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1023,7 +1023,7 @@ static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
   Cond.push_back(LastInst.getOperand(1));
 }
 
-static unsigned getReverseOpcode(unsigned Opcode){
+static unsigned getReverseOpcode(unsigned Opcode) {
   switch (Opcode) {
   default:
     llvm_unreachable("Unexpected Opcode");

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https://github.com/llvm/llvm-project/pull/160653