[llvm] [RISCV] Add commutative support for Qualcomm uC Xqcicm extension (PR #160653)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 24 23:56:38 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: quic_hchandel (hchandel)
<details>
<summary>Changes</summary>
This is a follow-up to #<!-- -->145643. See https://github.com/llvm/llvm-project/pull/145643#issuecomment-3009300419.
---
Patch is 32.84 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/160653.diff
3 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+61)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td (+2-2)
- (modified) llvm/test/CodeGen/RISCV/xqcicm.ll (+373-128)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 0ed97c61ec78a..924c55ef3aa87 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1023,6 +1023,37 @@ static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
Cond.push_back(LastInst.getOperand(1));
}
+static unsigned getReverseOpcode(unsigned Opcode){
+ switch (Opcode) {
+ default:
+ llvm_unreachable("Unexpected Opcode");
+ case RISCV::QC_MVEQ:
+ return RISCV::QC_MVNE;
+ case RISCV::QC_MVNE:
+ return RISCV::QC_MVEQ;
+ case RISCV::QC_MVLT:
+ return RISCV::QC_MVGE;
+ case RISCV::QC_MVGE:
+ return RISCV::QC_MVLT;
+ case RISCV::QC_MVLTU:
+ return RISCV::QC_MVGEU;
+ case RISCV::QC_MVGEU:
+ return RISCV::QC_MVLTU;
+ case RISCV::QC_MVEQI:
+ return RISCV::QC_MVNEI;
+ case RISCV::QC_MVNEI:
+ return RISCV::QC_MVEQI;
+ case RISCV::QC_MVLTI:
+ return RISCV::QC_MVGEI;
+ case RISCV::QC_MVGEI:
+ return RISCV::QC_MVLTI;
+ case RISCV::QC_MVLTUI:
+ return RISCV::QC_MVGEUI;
+ case RISCV::QC_MVGEUI:
+ return RISCV::QC_MVLTUI;
+ }
+}
+
unsigned RISCVCC::getBrCond(RISCVCC::CondCode CC, unsigned SelectOpc) {
switch (SelectOpc) {
default:
@@ -3762,6 +3793,19 @@ bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
return false;
// Operands 1 and 2 are commutable, if we switch the opcode.
return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
+ case RISCV::QC_MVEQ:
+ case RISCV::QC_MVNE:
+ case RISCV::QC_MVLT:
+ case RISCV::QC_MVGE:
+ case RISCV::QC_MVLTU:
+ case RISCV::QC_MVGEU:
+ case RISCV::QC_MVEQI:
+ case RISCV::QC_MVNEI:
+ case RISCV::QC_MVLTI:
+ case RISCV::QC_MVGEI:
+ case RISCV::QC_MVLTUI:
+ case RISCV::QC_MVGEUI:
+ return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 4);
case RISCV::TH_MULA:
case RISCV::TH_MULAW:
case RISCV::TH_MULAH:
@@ -3974,6 +4018,23 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
return TargetInstrInfo::commuteInstructionImpl(WorkingMI, false, OpIdx1,
OpIdx2);
}
+ case RISCV::QC_MVEQ:
+ case RISCV::QC_MVNE:
+ case RISCV::QC_MVLT:
+ case RISCV::QC_MVGE:
+ case RISCV::QC_MVLTU:
+ case RISCV::QC_MVGEU:
+ case RISCV::QC_MVEQI:
+ case RISCV::QC_MVNEI:
+ case RISCV::QC_MVLTI:
+ case RISCV::QC_MVGEI:
+ case RISCV::QC_MVLTUI:
+ case RISCV::QC_MVGEUI: {
+ auto &WorkingMI = cloneIfNew(MI);
+ WorkingMI.setDesc(get(getReverseOpcode(MI.getOpcode())));
+ return TargetInstrInfo::commuteInstructionImpl(WorkingMI, false, OpIdx1,
+ OpIdx2);
+ }
case RISCV::PseudoCCMOVGPRNoX0:
case RISCV::PseudoCCMOVGPR: {
// CCMOV can be commuted by inverting the condition.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 808d9117a1746..99823d144a1a7 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -604,7 +604,7 @@ class QCILICC<bits<3> funct3, bits<2> funct2, DAGOperand InTyRs2, string opcodes
let Inst{31-25} = {simm, funct2};
}
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in
class QCIMVCC<bits<3> funct3, string opcodestr>
: RVInstR4<0b00, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb),
(ins GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, GPRNoX0:$rs3),
@@ -612,7 +612,7 @@ class QCIMVCC<bits<3> funct3, string opcodestr>
let Constraints = "$rd = $rd_wb";
}
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in
class QCIMVCCI<bits<3> funct3, string opcodestr, DAGOperand immType>
: RVInstR4<0b10, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb),
(ins GPRNoX0:$rd, GPRNoX0:$rs1, immType:$imm, GPRNoX0:$rs3),
diff --git a/llvm/test/CodeGen/RISCV/xqcicm.ll b/llvm/test/CodeGen/RISCV/xqcicm.ll
index 1741be742323d..fb48301b1d8e8 100644
--- a/llvm/test/CodeGen/RISCV/xqcicm.ll
+++ b/llvm/test/CodeGen/RISCV/xqcicm.ll
@@ -23,15 +23,15 @@ define i32 @select_example(i32 %cond, i32 %x, i32 %y) {
; RV32IXQCICM-LABEL: select_example:
; RV32IXQCICM: # %bb.0: # %entry
; RV32IXQCICM-NEXT: andi a0, a0, 1
-; RV32IXQCICM-NEXT: qc.mvnei a2, a0, 0, a1
-; RV32IXQCICM-NEXT: mv a0, a2
+; RV32IXQCICM-NEXT: qc.mveqi a1, a0, 0, a2
+; RV32IXQCICM-NEXT: mv a0, a1
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_example:
; RV32IXQCI: # %bb.0: # %entry
; RV32IXQCI-NEXT: andi a0, a0, 1
-; RV32IXQCI-NEXT: qc.mvnei a2, a0, 0, a1
-; RV32IXQCI-NEXT: mv a0, a2
+; RV32IXQCI-NEXT: qc.mveqi a1, a0, 0, a2
+; RV32IXQCI-NEXT: mv a0, a1
; RV32IXQCI-NEXT: ret
entry:
%cond_trunc = trunc i32 %cond to i1
@@ -52,14 +52,14 @@ define i32 @select_cc_example_eq(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_eq:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mveqi a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvnei a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_eq:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mveqi a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %a, 11
@@ -80,14 +80,14 @@ define i32 @select_cc_example_eq1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_eq1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mveqi a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvnei a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_eq1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mveqi a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvnei a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 11, %a
@@ -108,14 +108,14 @@ define i32 @select_cc_example_ne(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ne:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvnei a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mveqi a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ne:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvnei a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mveqi a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %a, 11
@@ -136,14 +136,14 @@ define i32 @select_cc_example_ne1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ne1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvnei a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mveqi a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ne1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvnei a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mveqi a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 11, %a
@@ -164,14 +164,14 @@ define i32 @select_cc_example_slt(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_slt:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlti a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgei a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_slt:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvlti a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgei a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp slt i32 %a, 11
@@ -192,14 +192,14 @@ define i32 @select_cc_example_slt1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_slt1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgei a3, a0, 12, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvlti a2, a0, 12, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_slt1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgei a3, a0, 12, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvlti a2, a0, 12, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp slt i32 11, %a
@@ -220,14 +220,14 @@ define i32 @select_cc_example_sle(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sle:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlti a3, a0, 12, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgei a2, a0, 12, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_sle:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvlti a3, a0, 12, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgei a2, a0, 12, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sle i32 %a, 11
@@ -248,14 +248,14 @@ define i32 @select_cc_example_sle1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sle1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgei a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvlti a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_sle1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgei a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvlti a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sle i32 11, %a
@@ -276,14 +276,14 @@ define i32 @select_cc_example_sgt(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sgt:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgei a3, a0, 12, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvlti a2, a0, 12, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_sgt:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgei a3, a0, 12, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvlti a2, a0, 12, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sgt i32 %a, 11
@@ -304,14 +304,14 @@ define i32 @select_cc_example_sgt1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sgt1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlti a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgei a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_sgt1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvlti a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgei a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sgt i32 11, %a
@@ -332,14 +332,14 @@ define i32 @select_cc_example_sge(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sge:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgei a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvlti a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_sge:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgei a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvlti a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sge i32 %a, 11
@@ -360,14 +360,14 @@ define i32 @select_cc_example_sge1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_sge1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlti a3, a0, 12, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgei a2, a0, 12, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_sge1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvlti a3, a0, 12, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgei a2, a0, 12, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp sge i32 11, %a
@@ -388,14 +388,14 @@ define i32 @select_cc_example_ule(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ule:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltui a3, a0, 12, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgeui a2, a0, 12, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ule:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvltui a3, a0, 12, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgeui a2, a0, 12, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ule i32 %a, 11
@@ -416,14 +416,14 @@ define i32 @select_cc_example_ule1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ule1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgeui a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvltui a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ule1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgeui a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvltui a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ule i32 11, %a
@@ -444,14 +444,14 @@ define i32 @select_cc_example_ugt(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ugt:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgeui a3, a0, 12, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvltui a2, a0, 12, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ugt:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgeui a3, a0, 12, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvltui a2, a0, 12, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ugt i32 %a, 11
@@ -472,14 +472,14 @@ define i32 @select_cc_example_ugt1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ugt1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltui a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgeui a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ugt1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvltui a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgeui a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ugt i32 11, %a
@@ -500,14 +500,14 @@ define i32 @select_cc_example_ult(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ult:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltui a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgeui a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ult:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvltui a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgeui a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ult i32 %a, 11
@@ -528,14 +528,14 @@ define i32 @select_cc_example_ult1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ult1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgeui a3, a0, 12, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvltui a2, a0, 12, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ult1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgeui a3, a0, 12, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvltui a2, a0, 12, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ult i32 11, %a
@@ -556,14 +556,14 @@ define i32 @select_cc_example_uge(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_uge:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvgeui a3, a0, 11, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvltui a2, a0, 11, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_uge:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvgeui a3, a0, 11, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvltui a2, a0, 11, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp uge i32 %a, 11
@@ -584,14 +584,14 @@ define i32 @select_cc_example_uge1(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_uge1:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvltui a3, a0, 12, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvgeui a2, a0, 12, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_uge1:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvltui a3, a0, 12, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvgeui a2, a0, 12, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp uge i32 11, %a
@@ -611,14 +611,14 @@ define i32 @select_cc_example_eq_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_eq_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mveq a3, a0, a1, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvne a2, a0, a1, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_eq_reg:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mveq a3, a0, a1, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvne a2, a0, a1, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp eq i32 %a, %b
@@ -638,14 +638,14 @@ define i32 @select_cc_example_ne_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_ne_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvne a3, a0, a1, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mveq a2, a0, a1, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_ne_reg:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvne a3, a0, a1, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mveq a2, a0, a1, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%cmp = icmp ne i32 %a, %b
@@ -665,14 +665,14 @@ define i32 @select_cc_example_slt_reg(i32 %a, i32 %b, i32 %x, i32 %y) {
;
; RV32IXQCICM-LABEL: select_cc_example_slt_reg:
; RV32IXQCICM: # %bb.0: # %entry
-; RV32IXQCICM-NEXT: qc.mvlt a3, a0, a1, a2
-; RV32IXQCICM-NEXT: mv a0, a3
+; RV32IXQCICM-NEXT: qc.mvge a2, a0, a1, a3
+; RV32IXQCICM-NEXT: mv a0, a2
; RV32IXQCICM-NEXT: ret
;
; RV32IXQCI-LABEL: select_cc_example_slt_reg:
; RV32IXQCI: # %bb.0: # %entry
-; RV32IXQCI-NEXT: qc.mvlt a3, a0, a1, a2
-; RV32IXQCI-NEXT: mv a0, a3
+; RV32IXQCI-NEXT: qc.mvge a2, a0, a1, a3
+; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: ret
entry:
%c...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/160653
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