[llvm] [InstCombine] Rotate transformation port from SelectionDAG to InstCombine (PR #160628)

Axel Sorenson via llvm-commits llvm-commits at lists.llvm.org
Wed Sep 24 20:32:32 PDT 2025


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@@ -2405,6 +2405,24 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
               matchBSwapOrBitReverse(*II, /*MatchBSwaps*/ true,
                                      /*MatchBitReversals*/ true))
         return BitOp;
+
+      // R = fshl(X, X, C2)
+      // fshl(R, R, C1) --> fshl(X, X, (C1 + C2) % bitsize)
+      Value *InnerOp0;
+      Value *InnerOp1;
+      Constant *ShAmtInnerC;
+      if (match(Op0, m_FShl(m_Value(InnerOp0), m_Value(InnerOp1),
----------------
axelcool1234 wrote:

Thanks. I had tried `m_Specific` previously (I didn't know `m_Deferred` existed), which didn't work.

https://github.com/llvm/llvm-project/pull/160628


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