[llvm] [AMDGPU] Register allocation anti-hints to reduce MFMA hazard NOPs (PR #156943)

[Matt Arsenault via llvm-commits]

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@@ -676,3 +677,29 @@ bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const {
   }
   return false;
 }
+
+void MachineRegisterInfo::getPhysRegAntiHints(
+    Register VReg, SmallVectorImpl<MCPhysReg> &PhysAntiHints,
+    const VirtRegMap *VRM) const {
+  assert(VReg.isVirtual());
+  if (!AntiHintRegs.inBounds(VReg) || !VRM)
+    return;
+
+  const auto &AntiHints = AntiHintRegs[VReg];
+  const TargetRegisterInfo *TRI = getTargetRegisterInfo();
+
+  for (Register AntiHintVReg : AntiHints) {
+    // Check if the anti-hinted register has been allocated
+    if (VRM->hasPhys(AntiHintVReg)) {
+      MCPhysReg PhysReg = VRM->getPhys(AntiHintVReg);
+      // Add the physical register and all its aliases
+      for (MCRegAliasIterator AI(PhysReg, TRI, true); AI.isValid(); ++AI) {
+        PhysAntiHints.push_back(*AI);
+      }
+    }
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arsenm wrote:

This code should not be trying to handle register aliases, just return the raw value. How to treat aliases is context dependent 

https://github.com/llvm/llvm-project/pull/156943