[llvm] [ARM] LHS and RHS should be frozen for LowerCMP (PR #159993)

[via llvm-commits]

https://github.com/AZero13 updated https://github.com/llvm/llvm-project/pull/159993

>From 89d5baa45c7cb07451204559ce5c9aee581d6401 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sun, 21 Sep 2025 13:38:48 -0400
Subject: [PATCH] [ARM] LHS and RHS should be frozen for LowerCMP

LHS and RHS are used multiple times.
---
 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp |  4 ++--
 llvm/lib/Target/ARM/ARMISelLowering.cpp          | 13 +++++--------
 2 files changed, 7 insertions(+), 10 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 80500e48351e4..02f85cfc9262e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -10956,8 +10956,8 @@ SDValue TargetLowering::expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const {
 
 SDValue TargetLowering::expandCMP(SDNode *Node, SelectionDAG &DAG) const {
   unsigned Opcode = Node->getOpcode();
-  SDValue LHS = Node->getOperand(0);
-  SDValue RHS = Node->getOperand(1);
+  SDValue LHS = DAG.getFreeze(Node->getOperand(0));
+  SDValue RHS = DAG.getFreeze(Node->getOperand(1));
   EVT VT = LHS.getValueType();
   EVT ResVT = Node->getValueType(0);
   EVT BoolVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 9052cbfa89deb..01ab006d288fa 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -10479,6 +10479,9 @@ SDValue ARMTargetLowering::LowerCMP(SDValue Op, SelectionDAG &DAG) const {
 
   // Special case for Thumb1 UCMP only
   if (!IsSigned && Subtarget->isThumb1Only()) {
+    LHS = DAG.getFreeze(LHS);
+    RHS = DAG.getFreeze(RHS);
+
     // For Thumb unsigned comparison, use this sequence:
     // subs r2, r0, r1   ; r2 = LHS - RHS, sets flags
     // sbc r2, r2        ; r2 = r2 - r2 - !carry
@@ -10511,10 +10514,7 @@ SDValue ARMTargetLowering::LowerCMP(SDValue Op, SelectionDAG &DAG) const {
     // Final subtraction: Sbc1Result - Sbc2Result (no flags needed)
     SDValue Result =
         DAG.getNode(ISD::SUB, dl, MVT::i32, Sbc1Result, Sbc2Result);
-    if (Op.getValueType() != MVT::i32)
-      Result = DAG.getSExtOrTrunc(Result, dl, Op.getValueType());
-
-    return Result;
+    return DAG.getSExtOrTrunc(Result, dl, Op.getValueType());
   }
 
   // For the ARM assembly pattern:
@@ -10582,10 +10582,7 @@ SDValue ARMTargetLowering::LowerCMP(SDValue Op, SelectionDAG &DAG) const {
   SDValue Result2 = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, Result1, MinusOne,
                                 LTCondValue, Flags);
 
-  if (Op.getValueType() != MVT::i32)
-    Result2 = DAG.getSExtOrTrunc(Result2, dl, Op.getValueType());
-
-  return Result2;
+  return DAG.getSExtOrTrunc(Result2, dl, Op.getValueType());
 }
 
 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {