[llvm] [NFC][RISCV] Move Zvfbf* relative stuffs to RISCVInstrInfoZvfbf.td (PR #159619)

[LLVM Continuous Integration via llvm-commits]

llvm-ci wrote:

LLVM Buildbot has detected a new failure on builder `ml-opt-devrel-x86-64` running on `ml-opt-devrel-x86-64-b1` while building `llvm` at step 5 "build-unified-tree".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/175/builds/25706

<details>
<summary>Here is the relevant piece of the build log for the reference</summary>

```
Step 5 (build-unified-tree) failure: build (failure)
...
5.863 [3367/64/529] Building AVRGenCallingConv.inc...
5.927 [3366/64/530] Building R600GenCallingConv.inc...
5.955 [3365/64/531] Building AVRGenAsmWriter.inc...
5.975 [3364/64/532] Building R600GenAsmWriter.inc...
6.023 [3363/64/533] Building AVRGenAsmMatcher.inc...
6.046 [3362/64/534] Building R600GenRegisterInfo.inc...
6.070 [3361/64/535] Building R600GenMCCodeEmitter.inc...
6.267 [3360/64/536] Building R600GenSubtargetInfo.inc...
6.302 [3359/64/537] Building R600GenDFAPacketizer.inc...
6.523 [3358/64/538] Building RISCVTargetParserDef.inc...
FAILED: include/llvm/TargetParser/RISCVTargetParserDef.inc /b/ml-opt-devrel-x86-64-b1/build/include/llvm/TargetParser/RISCVTargetParserDef.inc 
cd /b/ml-opt-devrel-x86-64-b1/build/include/llvm/TargetParser && /b/ml-opt-devrel-x86-64-b1/build/bin/llvm-min-tblgen -gen-riscv-target-def -I/b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/include/llvm/TargetParser -I/b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV -I/var/lib/buildbot/.local/lib/python3.7/site-packages/tensorflow/include -I/b/ml-opt-devrel-x86-64-b1/build/include -I/b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/include /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCV.td --write-if-changed -o RISCVTargetParserDef.inc -d RISCVTargetParserDef.inc.d && /usr/bin/cmake -E cmake_transform_depfile Ninja gccdepfile /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/include/llvm/TargetParser /b/ml-opt-devrel-x86-64-b1/build /b/ml-opt-devrel-x86-64-b1/build/include/llvm/TargetParser /b/ml-opt-devrel-x86-64-b1/build/include/llvm/TargetParser/RISCVTargetParserDef.inc.d /b/ml-opt-devrel-x86-64-b1/build/CMakeFiles/d/07a4a0a3b9e0824f6c570982f066c45d846c6d9d5b89765970de0ff10765fe44.d
Included from /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCV.td:36:
Included from /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.td:2344:
Included from /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoV.td:1842:
/b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td:39:19: error: Variable not defined: 'HasStdExtZvfbfmin'
let Predicates = [HasStdExtZvfbfmin] in {
                  ^
6.997 [3358/63/539] Building ARMGenMCPseudoLowering.inc...
7.346 [3358/62/540] Building ARMGenMCCodeEmitter.inc...
7.363 [3358/61/541] Building R600GenDAGISel.inc...
7.478 [3358/60/542] Building ARMGenSystemRegister.inc...
7.514 [3358/59/543] Building AVRGenDAGISel.inc...
7.535 [3358/58/544] Building ARMGenCallingConv.inc...
7.577 [3358/57/545] Building ARMGenRegisterBank.inc...
7.607 [3358/56/546] Building AArch64GenMCPseudoLowering.inc...
7.610 [3358/55/547] Building ARMGenDisassemblerTables.inc...
7.780 [3358/54/548] Building R600GenInstrInfo.inc...
7.783 [3358/53/549] Building ARMGenRegisterInfo.inc...
7.851 [3358/52/550] Building ARMGenAsmMatcher.inc...
7.899 [3358/51/551] Building ARMGenAsmWriter.inc...
8.015 [3358/50/552] Building AArch64GenSDNodeInfo.inc...
8.072 [3358/49/553] Building BPFGenAsmMatcher.inc...
8.091 [3358/48/554] Building AVRGenSDNodeInfo.inc...
8.115 [3358/47/555] Building AArch64GenPreLegalizeGICombiner.inc...
8.131 [3358/46/556] Building AArch64GenMCCodeEmitter.inc...
8.143 [3358/45/557] Building AArch64GenExegesis.inc...
8.190 [3358/44/558] Building AVRGenDisassemblerTables.inc...
8.231 [3358/43/559] Building AVRGenMCCodeEmitter.inc...
8.234 [3358/42/560] Building AArch64GenPostLegalizeGICombiner.inc...
8.322 [3358/41/561] Building AArch64GenO0PreLegalizeGICombiner.inc...
8.327 [3358/40/562] Building AVRGenRegisterInfo.inc...
8.375 [3358/39/563] Building AArch64GenPostLegalizeGILowering.inc...
8.413 [3358/38/564] Building AArch64GenDisassemblerTables.inc...
8.432 [3358/37/565] Building BPFGenCallingConv.inc...
8.499 [3358/36/566] Building AArch64GenCallingConv.inc...
8.553 [3358/35/567] Building ARMGenFastISel.inc...
8.559 [3358/34/568] Building AVRGenSubtargetInfo.inc...
8.655 [3358/33/569] Building BPFGenAsmWriter.inc...

```

</details>

https://github.com/llvm/llvm-project/pull/159619