[llvm] [NFC][RISCV] Move Zvfbf* relative stuffs to RISCVInstrInfoZvfbf.td (PR #159619)

[LLVM Continuous Integration via llvm-commits]

llvm-ci wrote:

LLVM Buildbot has detected a new failure on builder `ml-opt-dev-x86-64` running on `ml-opt-dev-x86-64-b2` while building `llvm` at step 5 "build-unified-tree".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/137/builds/25862

<details>
<summary>Here is the relevant piece of the build log for the reference</summary>

```
Step 5 (build-unified-tree) failure: build (failure)
...
3.091 [3368/64/495] Building ARMTargetParserDef.inc...
3.116 [3367/64/496] Building COFFOptions.inc...
4.121 [3366/64/497] Building AArch64TargetParserDef.inc...
5.642 [3365/64/498] Building R600GenMCCodeEmitter.inc...
5.668 [3364/64/499] Building AVRGenCallingConv.inc...
5.699 [3363/64/500] Building AVRGenAsmWriter.inc...
5.732 [3362/64/501] Building R600GenAsmWriter.inc...
5.891 [3361/64/502] Building AVRGenAsmMatcher.inc...
5.915 [3360/64/503] Building R600GenRegisterInfo.inc...
5.956 [3359/64/504] Building RISCVTargetParserDef.inc...
FAILED: include/llvm/TargetParser/RISCVTargetParserDef.inc /b/ml-opt-dev-x86-64-b1/build/include/llvm/TargetParser/RISCVTargetParserDef.inc 
cd /b/ml-opt-dev-x86-64-b1/build/include/llvm/TargetParser && /b/ml-opt-dev-x86-64-b1/build/bin/llvm-min-tblgen -gen-riscv-target-def -I/b/ml-opt-dev-x86-64-b1/llvm-project/llvm/include/llvm/TargetParser -I/b/ml-opt-dev-x86-64-b1/llvm-project/llvm/lib/Target/RISCV -I/b/ml-opt-dev-x86-64-b1/build/include -I/b/ml-opt-dev-x86-64-b1/llvm-project/llvm/include /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCV.td --write-if-changed -o RISCVTargetParserDef.inc -d RISCVTargetParserDef.inc.d && /usr/bin/cmake -E cmake_transform_depfile Ninja gccdepfile /b/ml-opt-dev-x86-64-b1/llvm-project/llvm /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/include/llvm/TargetParser /b/ml-opt-dev-x86-64-b1/build /b/ml-opt-dev-x86-64-b1/build/include/llvm/TargetParser /b/ml-opt-dev-x86-64-b1/build/include/llvm/TargetParser/RISCVTargetParserDef.inc.d /b/ml-opt-dev-x86-64-b1/build/CMakeFiles/d/3c00e5d895649683a18e7f71b69fb93729556b7b11caa74e89509e519481cb40.d
Included from /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCV.td:36:
Included from /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.td:2344:
Included from /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoV.td:1842:
/b/ml-opt-dev-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td:39:19: error: Variable not defined: 'HasStdExtZvfbfmin'
let Predicates = [HasStdExtZvfbfmin] in {
                  ^
6.000 [3359/63/505] Building R600GenCallingConv.inc...
6.128 [3359/62/506] Building R600GenDFAPacketizer.inc...
6.360 [3359/61/507] Building R600GenSubtargetInfo.inc...
6.771 [3359/60/508] Building ARMGenMCPseudoLowering.inc...
6.784 [3359/59/509] Building R600GenDAGISel.inc...
7.104 [3359/58/510] Building ARMGenCallingConv.inc...
7.269 [3359/57/511] Building ARMGenRegisterInfo.inc...
7.283 [3359/56/512] Building ARMGenMCCodeEmitter.inc...
7.292 [3359/55/513] Building AArch64GenMCPseudoLowering.inc...
7.327 [3359/54/514] Building AArch64GenSDNodeInfo.inc...
7.379 [3359/53/515] Building ARMGenDisassemblerTables.inc...
7.403 [3359/52/516] Building R600GenInstrInfo.inc...
7.430 [3359/51/517] Building ARMGenAsmWriter.inc...
7.435 [3359/50/518] Building AVRGenDAGISel.inc...
7.564 [3359/49/519] Building ARMGenSystemRegister.inc...
7.615 [3359/48/520] Building ARMGenRegisterBank.inc...
7.615 [3359/47/521] Building AArch64GenPostLegalizeGICombiner.inc...
7.631 [3359/46/522] Building ARMGenAsmMatcher.inc...
7.639 [3359/45/523] Building AArch64GenExegesis.inc...
7.742 [3359/44/524] Building AArch64GenPostLegalizeGILowering.inc...
7.899 [3359/43/525] Building AArch64GenO0PreLegalizeGICombiner.inc...
7.903 [3359/42/526] Building AVRGenMCCodeEmitter.inc...
7.907 [3359/41/527] Building AArch64GenPreLegalizeGICombiner.inc...
7.951 [3359/40/528] Building AVRGenSDNodeInfo.inc...
7.963 [3359/39/529] Building AVRGenDisassemblerTables.inc...
8.035 [3359/38/530] Building AVRGenSubtargetInfo.inc...
8.042 [3359/37/531] Building AVRGenRegisterInfo.inc...
8.060 [3359/36/532] Building AArch64GenCallingConv.inc...
8.124 [3359/35/533] Building AArch64GenDisassemblerTables.inc...
8.130 [3359/34/534] Building AArch64GenMCCodeEmitter.inc...
8.332 [3359/33/535] Building AArch64GenAsmWriter1.inc...

```

</details>

https://github.com/llvm/llvm-project/pull/159619