[llvm] [NFC][RISCV] Move Zvfbf* relative stuffs to RISCVInstrInfoZvfbf.td (PR #159619)

[LLVM Continuous Integration via llvm-commits]

llvm-ci wrote:

LLVM Buildbot has detected a new failure on builder `mlir-rocm-mi200` running on `mi200-buildbot` while building `llvm` at step 6 "build-check-mlir-build-only".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/177/builds/21192

<details>
<summary>Here is the relevant piece of the build log for the reference</summary>

```
Step 6 (build-check-mlir-build-only) failure: build (failure)
...
2.716 [3347/48/1771] Building R600GenMCCodeEmitter.inc...
2.776 [3347/47/1772] Building TestOps.h.inc...
2.802 [3347/46/1773] Building TestOps.cpp.inc...
2.819 [3347/45/1774] Building R600GenCallingConv.inc...
2.843 [3347/44/1775] Building R600GenRegisterInfo.inc...
2.843 [3347/43/1776] Building R600GenAsmWriter.inc...
2.920 [3347/42/1777] Building R600GenSubtargetInfo.inc...
2.984 [3347/41/1778] Building R600GenDFAPacketizer.inc...
3.043 [3347/40/1779] Building NVPTXGenRegisterInfo.inc...
3.132 [3347/39/1780] Building RISCVTargetParserDef.inc...
FAILED: include/llvm/TargetParser/RISCVTargetParserDef.inc /vol/worker/mi200-buildbot/mlir-rocm-mi200/build/include/llvm/TargetParser/RISCVTargetParserDef.inc 
cd /vol/worker/mi200-buildbot/mlir-rocm-mi200/build/include/llvm/TargetParser && /vol/worker/mi200-buildbot/mlir-rocm-mi200/build/bin/llvm-min-tblgen -gen-riscv-target-def -I/vol/worker/mi200-buildbot/mlir-rocm-mi200/llvm-project/llvm/include/llvm/TargetParser -I/vol/worker/mi200-buildbot/mlir-rocm-mi200/llvm-project/llvm/lib/Target/RISCV -I/vol/worker/mi200-buildbot/mlir-rocm-mi200/build/include -I/vol/worker/mi200-buildbot/mlir-rocm-mi200/llvm-project/llvm/include /vol/worker/mi200-buildbot/mlir-rocm-mi200/llvm-project/llvm/lib/Target/RISCV/RISCV.td --write-if-changed -o RISCVTargetParserDef.inc -d RISCVTargetParserDef.inc.d && /etc/cmake/bin/cmake -E cmake_transform_depfile Ninja gccdepfile /vol/worker/mi200-buildbot/mlir-rocm-mi200/llvm-project/llvm /vol/worker/mi200-buildbot/mlir-rocm-mi200/llvm-project/llvm/include/llvm/TargetParser /vol/worker/mi200-buildbot/mlir-rocm-mi200/build /vol/worker/mi200-buildbot/mlir-rocm-mi200/build/include/llvm/TargetParser /vol/worker/mi200-buildbot/mlir-rocm-mi200/build/include/llvm/TargetParser/RISCVTargetParserDef.inc.d /vol/worker/mi200-buildbot/mlir-rocm-mi200/build/CMakeFiles/d/b4fa209d607a0e9cdbac09bce1cf80f560ac43669443b07adf9b30556745fc03.d
Included from /vol/worker/mi200-buildbot/mlir-rocm-mi200/llvm-project/llvm/lib/Target/RISCV/RISCV.td:36:
Included from /vol/worker/mi200-buildbot/mlir-rocm-mi200/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.td:2344:
Included from /vol/worker/mi200-buildbot/mlir-rocm-mi200/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoV.td:1842:
/vol/worker/mi200-buildbot/mlir-rocm-mi200/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td:39:19: error: Variable not defined: 'HasStdExtZvfbfmin'
let Predicates = [HasStdExtZvfbfmin] in {
                  ^
3.168 [3347/38/1781] Building NVPTXGenSubtargetInfo.inc...
3.185 [3347/37/1782] Building NVPTXGenAsmWriter.inc...
3.236 [3347/36/1783] Building R600GenDAGISel.inc...
3.385 [3347/35/1784] Building R600GenInstrInfo.inc...
3.857 [3347/34/1785] Building NVPTXGenInstrInfo.inc...
3.931 [3347/33/1786] Building NVPTXGenDAGISel.inc...
4.625 [3347/32/1787] Building X86GenRegisterInfo.inc...
4.625 [3347/31/1788] Building X86GenRegisterBank.inc...
4.768 [3347/30/1789] Building X86GenMnemonicTables.inc...
4.966 [3347/29/1790] Building X86GenExegesis.inc...
5.141 [3347/28/1791] Building X86GenAsmWriter.inc...
5.152 [3347/27/1792] Building X86GenCallingConv.inc...
5.233 [3347/26/1793] Building X86GenAsmWriter1.inc...
5.458 [3347/25/1794] Building X86GenDisassemblerTables.inc...
5.508 [3347/24/1795] Building X86GenFoldTables.inc...
5.784 [3347/23/1796] Building X86GenInstrMapping.inc...
6.220 [3347/22/1797] Building X86GenAsmMatcher.inc...
7.876 [3347/21/1798] Building X86GenFastISel.inc...
8.522 [3347/20/1799] Building X86GenGlobalISel.inc...
9.964 [3347/19/1800] Building X86GenDAGISel.inc...
11.699 [3347/18/1801] Building X86GenSubtargetInfo.inc...
13.532 [3347/17/1802] Building X86GenInstrInfo.inc...
24.716 [3347/16/1803] Building AMDGPUGenMCPseudoLowering.inc...
25.428 [3347/15/1804] Building AMDGPUGenRegBankGICombiner.inc...
25.587 [3347/14/1805] Building AMDGPUGenPostLegalizeGICombiner.inc...
25.764 [3347/13/1806] Building AMDGPUGenPreLegalizeGICombiner.inc...
26.129 [3347/12/1807] Building AMDGPUGenSubtargetInfo.inc...
26.710 [3347/11/1808] Building AMDGPUGenDisassemblerTables.inc...
26.735 [3347/10/1809] Building AMDGPUGenMCCodeEmitter.inc...
27.320 [3347/9/1810] Building AMDGPUGenSearchableTables.inc...
39.761 [3347/8/1811] Building AMDGPUGenCallingConv.inc...

```

</details>

https://github.com/llvm/llvm-project/pull/159619