[llvm] [NFC][RISCV] Move Zvfbf* relative stuffs to RISCVInstrInfoZvfbf.td (PR #159619)

[LLVM Continuous Integration via llvm-commits]

llvm-ci wrote:

LLVM Buildbot has detected a new failure on builder `ml-opt-rel-x86-64` running on `ml-opt-rel-x86-64-b1` while building `llvm` at step 5 "build-unified-tree".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/185/builds/25705

<details>
<summary>Here is the relevant piece of the build log for the reference</summary>

```
Step 5 (build-unified-tree) failure: build (failure)
...
5.405 [3367/64/529] Building R600GenMCCodeEmitter.inc...
5.585 [3366/64/530] Building AVRGenCallingConv.inc...
5.594 [3365/64/531] Building R600GenCallingConv.inc...
5.741 [3364/64/532] Building AVRGenAsmMatcher.inc...
5.809 [3363/64/533] Building R600GenRegisterInfo.inc...
5.837 [3362/64/534] Building R600GenAsmWriter.inc...
5.937 [3361/64/535] Building AVRGenAsmWriter.inc...
6.141 [3360/64/536] Building R600GenSubtargetInfo.inc...
6.179 [3359/64/537] Building R600GenDFAPacketizer.inc...
6.542 [3358/64/538] Building RISCVTargetParserDef.inc...
FAILED: include/llvm/TargetParser/RISCVTargetParserDef.inc /b/ml-opt-rel-x86-64-b1/build/include/llvm/TargetParser/RISCVTargetParserDef.inc 
cd /b/ml-opt-rel-x86-64-b1/build/include/llvm/TargetParser && /b/ml-opt-rel-x86-64-b1/build/bin/llvm-min-tblgen -gen-riscv-target-def -I/b/ml-opt-rel-x86-64-b1/llvm-project/llvm/include/llvm/TargetParser -I/b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV -I/var/lib/buildbot/.local/lib/python3.7/site-packages/tensorflow/include -I/b/ml-opt-rel-x86-64-b1/build/include -I/b/ml-opt-rel-x86-64-b1/llvm-project/llvm/include /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCV.td --write-if-changed -o RISCVTargetParserDef.inc -d RISCVTargetParserDef.inc.d && /usr/bin/cmake -E cmake_transform_depfile Ninja gccdepfile /b/ml-opt-rel-x86-64-b1/llvm-project/llvm /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/include/llvm/TargetParser /b/ml-opt-rel-x86-64-b1/build /b/ml-opt-rel-x86-64-b1/build/include/llvm/TargetParser /b/ml-opt-rel-x86-64-b1/build/include/llvm/TargetParser/RISCVTargetParserDef.inc.d /b/ml-opt-rel-x86-64-b1/build/CMakeFiles/d/31295a842b8d944258ac67e23ac9195061e1a361ca3277bd9ee7e9c6bbe0ef92.d
Included from /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCV.td:36:
Included from /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfo.td:2344:
Included from /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoV.td:1842:
/b/ml-opt-rel-x86-64-b1/llvm-project/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td:39:19: error: Variable not defined: 'HasStdExtZvfbfmin'
let Predicates = [HasStdExtZvfbfmin] in {
                  ^
6.878 [3358/63/539] Building R600GenDAGISel.inc...
6.973 [3358/62/540] Building ARMGenRegisterBank.inc...
6.993 [3358/61/541] Building ARMGenCallingConv.inc...
7.008 [3358/60/542] Building ARMGenSystemRegister.inc...
7.061 [3358/59/543] Building ARMGenMCPseudoLowering.inc...
7.153 [3358/58/544] Building ARMGenMCCodeEmitter.inc...
7.217 [3358/57/545] Building ARMGenDisassemblerTables.inc...
7.409 [3358/56/546] Building AVRGenDisassemblerTables.inc...
7.463 [3358/55/547] Building AArch64GenExegesis.inc...
7.483 [3358/54/548] Building AVRGenRegisterInfo.inc...
7.529 [3358/53/549] Building ARMGenAsmWriter.inc...
7.565 [3358/52/550] Building R600GenInstrInfo.inc...
7.584 [3358/51/551] Building AArch64GenMCPseudoLowering.inc...
7.613 [3358/50/552] Building AArch64GenSDNodeInfo.inc...
7.634 [3358/49/553] Building ARMGenRegisterInfo.inc...
7.733 [3358/48/554] Building AVRGenMCCodeEmitter.inc...
7.825 [3358/47/555] Building ARMGenAsmMatcher.inc...
7.826 [3358/46/556] Building AArch64GenO0PreLegalizeGICombiner.inc...
7.852 [3358/45/557] Building AVRGenDAGISel.inc...
7.901 [3358/44/558] Building AVRGenSDNodeInfo.inc...
8.009 [3358/43/559] Building AArch64GenPostLegalizeGILowering.inc...
8.023 [3358/42/560] Building AArch64GenPreLegalizeGICombiner.inc...
8.111 [3358/41/561] Building AArch64GenPostLegalizeGICombiner.inc...
8.136 [3358/40/562] Building AArch64GenMCCodeEmitter.inc...
8.140 [3358/39/563] Building BPFGenAsmMatcher.inc...
8.184 [3358/38/564] Building BPFGenAsmWriter.inc...
8.269 [3358/37/565] Building AArch64GenCallingConv.inc...
8.325 [3358/36/566] Building AVRGenSubtargetInfo.inc...
8.329 [3358/35/567] Building AArch64GenDisassemblerTables.inc...
8.385 [3358/34/568] Building BPFGenCallingConv.inc...
8.483 [3358/33/569] Building AArch64GenRegisterBank.inc...

```

</details>

https://github.com/llvm/llvm-project/pull/159619