[llvm] [RISCV] Update floating point load latency in SiFive7 scheduling model (PR #159462)

Pengcheng Wang via llvm-commits llvm-commits at lists.llvm.org
Wed Sep 17 20:28:00 PDT 2025

Previous message: [llvm] [RISCV] Add MVendorID, MArchID, and MImpID for sifive-p550. (PR #159465)
Next message: [llvm] [RISCV] Update floating point load latency in SiFive7 scheduling model (PR #159462)
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

https://github.com/wangpc-pp approved this pull request.

LGTM.

https://github.com/llvm/llvm-project/pull/159462

Previous message: [llvm] [RISCV] Add MVendorID, MArchID, and MImpID for sifive-p550. (PR #159465)
Next message: [llvm] [RISCV] Update floating point load latency in SiFive7 scheduling model (PR #159462)
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list