[llvm] [llvm][RISCV] Implement Zilsd load/store pair optimization (PR #158640)

[Sam Elliott via llvm-commits]

lenary wrote:

> > To me it feels more similar to an intermediate scalar alignment mode, somewhere between "everything has to be naturally aligned" (the default) and `FeatureUnalignedScalarMem` (everything can be 1-byte aligned) - maybe it should be modelled that way?
> 
> Wouldn't modeling it that way imply that FLD and FSD would support 4 byte alignment when Zilsd supports 4 byte alignment?

Fair question, but my feeling (no hard data to back this up) is that cores with the 4-byte Zilsd support would likely do the same kind of thing for D accesses. I would especially expect this for Zdinx cores.

If we do make it an unaligned scalar mode, I would probably rename it `XLenAlignedScalarMem`.

Maybe this is too much and a zilsd-only option is good enough for the moment.

https://github.com/llvm/llvm-project/pull/158640