[llvm] [llvm][RISCV] Implement Zilsd load/store pair optimization (PR #158640)

[Craig Topper via llvm-commits]

topperc wrote:

> To me it feels more similar to an intermediate scalar alignment mode, somewhere between "everything has to be naturally aligned" (the default) and `FeatureUnalignedScalarMem` (everything can be 1-byte aligned) - maybe it should be modelled that way?

Wouldn't modeling it that way imply that FLD and FSD would support 4 byte alignment when Zilsd supports 4 byte alignment?

https://github.com/llvm/llvm-project/pull/158640