[llvm] [TableGen] Add mapping from processor ID to resource index for packetizer (PR #158182)
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llvm-commits at lists.llvm.org
Mon Sep 15 04:27:18 PDT 2025
https://github.com/LuoYuanke updated https://github.com/llvm/llvm-project/pull/158182
>From 5aa048c1adfa9d12a384e2cdf2754e919814ecc3 Mon Sep 17 00:00:00 2001
From: Yuanke Luo <ykluo at birentech.com>
Date: Thu, 11 Sep 2025 19:57:20 +0800
Subject: [PATCH 1/3] [TableGen] Add mapping from processor ID to resource
index for packetizer
Tablegen would generate code to access TargetResourceIndices with processor ID.
The TargetProcResourceIndexStart[] array is generated for each processor which
has itineraries. The processor which doesn't has itineraries is excluded from
the array. When a target has mixed processors, the processor ID may exceed the
array size and cause the error.
This patch is to generate a table mapping processor with itineraries to resource
index, so that scheduler can get the correct resource index with processor ID.
---
llvm/test/TableGen/DFAPacketizer.td | 31 ++++++++++++++++++++
llvm/utils/TableGen/DFAPacketizerEmitter.cpp | 19 +++++++++---
2 files changed, 46 insertions(+), 4 deletions(-)
create mode 100644 llvm/test/TableGen/DFAPacketizer.td
diff --git a/llvm/test/TableGen/DFAPacketizer.td b/llvm/test/TableGen/DFAPacketizer.td
new file mode 100644
index 0000000000000..b4c05c63811b5
--- /dev/null
+++ b/llvm/test/TableGen/DFAPacketizer.td
@@ -0,0 +1,31 @@
+// RUN: llvm-tblgen -gen-dfa-packetizer -I %p/../../include %s | FileCheck %s
+
+include "llvm/Target/Target.td"
+
+def TestTarget : Target;
+
+def TestSchedModel : SchedMachineModel {
+ let CompleteModel = 0;
+}
+
+def TestProcessor1 : ProcessorModel<"testprocessor1", TestSchedModel, []>;
+
+def FU0 : FuncUnit;
+def FU1 : FuncUnit;
+
+def OP0 : InstrItinClass;
+def OP1 : InstrItinClass;
+
+def Itin {
+ list<InstrItinData> ItinList = [
+ InstrItinData<OP0, [InstrStage<1, [FU0]>]>,
+ InstrItinData<OP1, [InstrStage<1, [FU1]>]>,
+ ];
+}
+
+// CHECK: std::map<unsigned, unsigned> TestTargetProcIdToResourceIndexStartMapping = {
+// CHECK-NEXT: { 2, 1 }, // TestItinerariesModel
+// CHECK-NEXT: };
+
+def TestItineraries: ProcessorItineraries<[], [], Itin.ItinList>;
+def TestProcessor2 : Processor<"testprocessor2", TestItineraries, []>;
diff --git a/llvm/utils/TableGen/DFAPacketizerEmitter.cpp b/llvm/utils/TableGen/DFAPacketizerEmitter.cpp
index 8cb2c22736f8a..0fd30411451a2 100644
--- a/llvm/utils/TableGen/DFAPacketizerEmitter.cpp
+++ b/llvm/utils/TableGen/DFAPacketizerEmitter.cpp
@@ -256,6 +256,16 @@ void DFAPacketizerEmitter::emitForItineraries(
}
OS << "\n};\n\n";
+ // Output the mapping from proc ID to ResourceIndexStart
+ Idx = 1;
+ OS << "std::map<unsigned, unsigned> " << TargetName << DFAName
+ << "ProcIdToResourceIndexStartMapping = {\n";
+ for (const CodeGenProcModel *Model : ProcModels) {
+ OS << " { " << Model->Index << ", " << Idx++ << " }, // "
+ << Model->ModelName << "\n";
+ }
+ OS << "};\n\n";
+
// And the mapping from Itinerary index into the previous table.
OS << "constexpr unsigned " << TargetName << DFAName
<< "ProcResourceIndexStart[] = {\n";
@@ -339,16 +349,17 @@ void DFAPacketizerEmitter::emitForItineraries(
std::string SubTargetClassName = TargetName + "GenSubtargetInfo";
OS << "namespace llvm {\n";
- OS << "DFAPacketizer *" << SubTargetClassName << "::"
- << "create" << DFAName
+ OS << "DFAPacketizer *" << SubTargetClassName << "::" << "create" << DFAName
<< "DFAPacketizer(const InstrItineraryData *IID) const {\n"
<< " static Automaton<uint64_t> A(ArrayRef<" << TargetAndDFAName
<< "Transition>(" << TargetAndDFAName << "Transitions), "
<< TargetAndDFAName << "TransitionInfo);\n"
+ << " unsigned Index = " << TargetName << DFAName
+ << "ProcIdToResourceIndexStartMapping[IID->SchedModel.ProcID];\n"
<< " unsigned ProcResIdxStart = " << TargetAndDFAName
- << "ProcResourceIndexStart[IID->SchedModel.ProcID];\n"
+ << "ProcResourceIndexStart[Index];\n"
<< " unsigned ProcResIdxNum = " << TargetAndDFAName
- << "ProcResourceIndexStart[IID->SchedModel.ProcID + 1] - "
+ << "ProcResourceIndexStart[Index + 1] - "
"ProcResIdxStart;\n"
<< " return new DFAPacketizer(IID, A, {&" << TargetAndDFAName
<< "ResourceIndices[ProcResIdxStart], ProcResIdxNum});\n"
>From 637d55d2fcdd3c7530079964f56baf3b05893e99 Mon Sep 17 00:00:00 2001
From: Yuanke Luo <ykluo at birentech.com>
Date: Mon, 15 Sep 2025 15:40:22 +0800
Subject: [PATCH 2/3] [TableGen] Address Matt and Haohai's comments
---
llvm/test/TableGen/DFAPacketizer.td | 26 ++++++++++--
llvm/utils/TableGen/DFAPacketizerEmitter.cpp | 44 +++++++++++++++-----
2 files changed, 56 insertions(+), 14 deletions(-)
diff --git a/llvm/test/TableGen/DFAPacketizer.td b/llvm/test/TableGen/DFAPacketizer.td
index b4c05c63811b5..2d7182b907a47 100644
--- a/llvm/test/TableGen/DFAPacketizer.td
+++ b/llvm/test/TableGen/DFAPacketizer.td
@@ -23,9 +23,29 @@ def Itin {
];
}
-// CHECK: std::map<unsigned, unsigned> TestTargetProcIdToResourceIndexStartMapping = {
-// CHECK-NEXT: { 2, 1 }, // TestItinerariesModel
-// CHECK-NEXT: };
+// CHECK: int TestTargetGetResourceIndex(unsigned ProcID) {
+// CHECK-NEXT: static const unsigned TestTargetProcIdToProcResourceIdxTable[][2] = {
+// CHECK-NEXT: { 2, 1 }, // TestItinerariesModel
+// CHECK-NEXT: };
+// CHECK-NEXT: unsigned Mid;
+// CHECK-NEXT: unsigned Start = 0;
+// CHECK-NEXT: unsigned End = 1;
+// CHECK-NEXT: while (Start < End) {
+// CHECK-NEXT: Mid = Start + (End - Start) / 2;
+// CHECK-NEXT: if (ProcID == TestTargetProcIdToProcResourceIdxTable[Mid][0]) {
+// CHECK-NEXT: break;
+// CHECK-NEXT: }
+// CHECK-NEXT: if (ProcID < TestTargetProcIdToProcResourceIdxTable[Mid][0])
+// CHECK-NEXT: End = Mid;
+// CHECK-NEXT: else
+// CHECK-NEXT: Start = Mid + 1;
+// CHECK-NEXT: }
+// CHECK-NEXT: if (Start == End)
+// CHECK-NEXT: return -1; // Didn't find
+// CHECK-NEXT: return TestTargetProcIdToProcResourceIdxTable[Mid][1];
+// CHECK-NEXT: }
+
+// CHECK: unsigned Index = TestTargetGetResourceIndex(IID->SchedModel.ProcID);
def TestItineraries: ProcessorItineraries<[], [], Itin.ItinList>;
def TestProcessor2 : Processor<"testprocessor2", TestItineraries, []>;
diff --git a/llvm/utils/TableGen/DFAPacketizerEmitter.cpp b/llvm/utils/TableGen/DFAPacketizerEmitter.cpp
index 0fd30411451a2..b7fdf05a7e544 100644
--- a/llvm/utils/TableGen/DFAPacketizerEmitter.cpp
+++ b/llvm/utils/TableGen/DFAPacketizerEmitter.cpp
@@ -256,16 +256,6 @@ void DFAPacketizerEmitter::emitForItineraries(
}
OS << "\n};\n\n";
- // Output the mapping from proc ID to ResourceIndexStart
- Idx = 1;
- OS << "std::map<unsigned, unsigned> " << TargetName << DFAName
- << "ProcIdToResourceIndexStartMapping = {\n";
- for (const CodeGenProcModel *Model : ProcModels) {
- OS << " { " << Model->Index << ", " << Idx++ << " }, // "
- << Model->ModelName << "\n";
- }
- OS << "};\n\n";
-
// And the mapping from Itinerary index into the previous table.
OS << "constexpr unsigned " << TargetName << DFAName
<< "ProcResourceIndexStart[] = {\n";
@@ -276,6 +266,38 @@ void DFAPacketizerEmitter::emitForItineraries(
}
OS << " " << ScheduleClasses.size() << "\n};\n\n";
+ // Output the mapping from proc ID to ResourceIndexStart
+ Idx = 1;
+ OS << "int " << TargetName << DFAName
+ << "GetResourceIndex(unsigned ProcID) { \n"
+ << " static const unsigned " << TargetName << DFAName
+ << "ProcIdToProcResourceIdxTable[][2] = {\n";
+ for (const CodeGenProcModel *Model : ProcModels) {
+ OS << " { " << Model->Index << ", " << Idx++ << " }, // "
+ << Model->ModelName << "\n";
+ }
+ OS << " };\n"
+ << " unsigned Mid;\n"
+ << " unsigned Start = 0;\n"
+ << " unsigned End = " << ProcModels.size() << ";\n"
+ << " while (Start < End) {\n"
+ << " Mid = Start + (End - Start) / 2;\n"
+ << " if (ProcID == " << TargetName << DFAName
+ << "ProcIdToProcResourceIdxTable[Mid][0]) {\n"
+ << " break;\n"
+ << " }\n"
+ << " if (ProcID < " << TargetName << DFAName
+ << "ProcIdToProcResourceIdxTable[Mid][0])\n"
+ << " End = Mid;\n"
+ << " else\n"
+ << " Start = Mid + 1;\n"
+ << " }\n"
+ << " if (Start == End)\n"
+ << " return -1; // Didn't find\n"
+ << " return " << TargetName << DFAName
+ << "ProcIdToProcResourceIdxTable[Mid][1];\n"
+ << "}\n\n";
+
// The type of a state in the nondeterministic automaton we're defining.
using NfaStateTy = uint64_t;
@@ -355,7 +377,7 @@ void DFAPacketizerEmitter::emitForItineraries(
<< "Transition>(" << TargetAndDFAName << "Transitions), "
<< TargetAndDFAName << "TransitionInfo);\n"
<< " unsigned Index = " << TargetName << DFAName
- << "ProcIdToResourceIndexStartMapping[IID->SchedModel.ProcID];\n"
+ << "GetResourceIndex(IID->SchedModel.ProcID);\n"
<< " unsigned ProcResIdxStart = " << TargetAndDFAName
<< "ProcResourceIndexStart[Index];\n"
<< " unsigned ProcResIdxNum = " << TargetAndDFAName
>From b50de6cba354a8c1fe00e6a83068e0c550486356 Mon Sep 17 00:00:00 2001
From: Yuanke Luo <ykluo at birentech.com>
Date: Mon, 15 Sep 2025 19:11:34 +0800
Subject: [PATCH 3/3] [TableGen] Address Haohai's comments
---
llvm/test/TableGen/DFAPacketizer.td | 21 ++++-------------
llvm/utils/TableGen/DFAPacketizerEmitter.cpp | 24 ++++----------------
2 files changed, 10 insertions(+), 35 deletions(-)
diff --git a/llvm/test/TableGen/DFAPacketizer.td b/llvm/test/TableGen/DFAPacketizer.td
index 2d7182b907a47..dd3b08ef4d77d 100644
--- a/llvm/test/TableGen/DFAPacketizer.td
+++ b/llvm/test/TableGen/DFAPacketizer.td
@@ -27,22 +27,11 @@ def Itin {
// CHECK-NEXT: static const unsigned TestTargetProcIdToProcResourceIdxTable[][2] = {
// CHECK-NEXT: { 2, 1 }, // TestItinerariesModel
// CHECK-NEXT: };
-// CHECK-NEXT: unsigned Mid;
-// CHECK-NEXT: unsigned Start = 0;
-// CHECK-NEXT: unsigned End = 1;
-// CHECK-NEXT: while (Start < End) {
-// CHECK-NEXT: Mid = Start + (End - Start) / 2;
-// CHECK-NEXT: if (ProcID == TestTargetProcIdToProcResourceIdxTable[Mid][0]) {
-// CHECK-NEXT: break;
-// CHECK-NEXT: }
-// CHECK-NEXT: if (ProcID < TestTargetProcIdToProcResourceIdxTable[Mid][0])
-// CHECK-NEXT: End = Mid;
-// CHECK-NEXT: else
-// CHECK-NEXT: Start = Mid + 1;
-// CHECK-NEXT: }
-// CHECK-NEXT: if (Start == End)
-// CHECK-NEXT: return -1; // Didn't find
-// CHECK-NEXT: return TestTargetProcIdToProcResourceIdxTable[Mid][1];
+// CHECK-NEXT: auto It = std::lower_bound(
+// CHECK-NEXT: std::begin(TestTargetProcIdToProcResourceIdxTable),
+// CHECK-NEXT: std::end(TestTargetProcIdToProcResourceIdxTable), ProcID,
+// CHECK-NEXT: [](const unsigned LHS[], unsigned Val) { return LHS[0] < Val; });
+// CHECK-NEXT: return (*It)[1];
// CHECK-NEXT: }
// CHECK: unsigned Index = TestTargetGetResourceIndex(IID->SchedModel.ProcID);
diff --git a/llvm/utils/TableGen/DFAPacketizerEmitter.cpp b/llvm/utils/TableGen/DFAPacketizerEmitter.cpp
index b7fdf05a7e544..c8816423cf34b 100644
--- a/llvm/utils/TableGen/DFAPacketizerEmitter.cpp
+++ b/llvm/utils/TableGen/DFAPacketizerEmitter.cpp
@@ -277,25 +277,11 @@ void DFAPacketizerEmitter::emitForItineraries(
<< Model->ModelName << "\n";
}
OS << " };\n"
- << " unsigned Mid;\n"
- << " unsigned Start = 0;\n"
- << " unsigned End = " << ProcModels.size() << ";\n"
- << " while (Start < End) {\n"
- << " Mid = Start + (End - Start) / 2;\n"
- << " if (ProcID == " << TargetName << DFAName
- << "ProcIdToProcResourceIdxTable[Mid][0]) {\n"
- << " break;\n"
- << " }\n"
- << " if (ProcID < " << TargetName << DFAName
- << "ProcIdToProcResourceIdxTable[Mid][0])\n"
- << " End = Mid;\n"
- << " else\n"
- << " Start = Mid + 1;\n"
- << " }\n"
- << " if (Start == End)\n"
- << " return -1; // Didn't find\n"
- << " return " << TargetName << DFAName
- << "ProcIdToProcResourceIdxTable[Mid][1];\n"
+ << " auto It = std::lower_bound(\n"
+ << " std::begin(" << TargetName << DFAName << "ProcIdToProcResourceIdxTable),\n"
+ << " std::end(" << TargetName << DFAName << "ProcIdToProcResourceIdxTable), ProcID,\n"
+ << " [](const unsigned LHS[], unsigned Val) { return LHS[0] < Val; });\n"
+ << " return (*It)[1];\n"
<< "}\n\n";
// The type of a state in the nondeterministic automaton we're defining.
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