[llvm] [AMDGPU] Fix vector legalization for bf16 valu ops (PR #158439)

[Matt Arsenault via llvm-commits]

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@@ -850,6 +850,13 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::SELECT, {MVT::v4i16, MVT::v4f16, MVT::v4bf16},
                        Custom);
 
+    if (Subtarget->hasBF16PackedInsts()) {
+      for (MVT VT : {MVT::v4bf16, MVT::v8bf16, MVT::v16bf16, MVT::v32bf16})
+        // Split vector operations.
+        setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA, ISD::FCANONICALIZE},
+                           VT, Custom);
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arsenm wrote:

Test coverage isn't comprehensive across all types + opcodes 

https://github.com/llvm/llvm-project/pull/158439