[llvm] [AMDGPU] Support lowering of cluster related instrinsics (PR #157978)
Shilei Tian via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 11 13:34:59 PDT 2025
================
@@ -7415,6 +7552,22 @@ bool AMDGPULegalizerInfo::legalizeWaveID(MachineInstr &MI,
return true;
}
+bool AMDGPULegalizerInfo::legalizeConstHwRegRead(MachineInstr &MI,
+ MachineIRBuilder &B,
+ AMDGPU::Hwreg::Id HwReg,
+ unsigned LowBit,
+ unsigned Width) const {
+ MachineRegisterInfo &MRI = *B.getMRI();
+ Register DstReg = MI.getOperand(0).getReg();
+ if (!MRI.getRegClassOrNull(DstReg))
+ MRI.setRegClass(DstReg, &AMDGPU::SReg_32RegClass);
----------------
shiltian wrote:
> Move this directly to selection then?
Which part?
> Also use the normal constraint function.
What is the normal constraint function?
https://github.com/llvm/llvm-project/pull/157978
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