[llvm] [InstCombine] Canonicalize active lane mask params (PR #158065)

[Matthew Devereau via llvm-commits]

https://github.com/MDevereau updated https://github.com/llvm/llvm-project/pull/158065

>From e3dd490906b456f0e1f92df5de0858f08abf596b Mon Sep 17 00:00:00 2001
From: Matthew Devereau <matthew.devereau at arm.com>
Date: Wed, 27 Aug 2025 16:09:43 +0000
Subject: [PATCH] [InstCombine] Canonicalize active lane mask params

Rewrite active lane mask intrinsics to begin their range
from 0 when both parameters are constant integers.
---
 .../InstCombine/InstCombineCalls.cpp          | 14 +++++
 .../InstCombine/get_active_lane_mask.ll       | 54 +++++++++++++++++++
 2 files changed, 68 insertions(+)
 create mode 100644 llvm/test/Transforms/InstCombine/get_active_lane_mask.ll

diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
index 33b66aeaffe60..c6f6f51b58b41 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
@@ -3925,6 +3925,20 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
     }
     break;
   }
+  case Intrinsic::get_active_lane_mask: {
+    const APInt *Op0, *Op1;
+    if (match(II->getOperand(0), m_Zero()) ||
+        !match(II->getOperand(0), m_APInt(Op0)) ||
+        !match(II->getOperand(1), m_APInt(Op1)))
+      break;
+
+    Type *OpTy = II->getOperand(0)->getType();
+    return replaceInstUsesWith(
+        *II,
+        Builder.CreateIntrinsic(II->getType(), Intrinsic::get_active_lane_mask,
+                                {Constant::getNullValue(OpTy),
+                                 ConstantInt::get(OpTy, Op1->usub_sat(*Op0))}));
+  }
   default: {
     // Handle target specific intrinsics
     std::optional<Instruction *> V = targetInstCombineIntrinsic(*II);
diff --git a/llvm/test/Transforms/InstCombine/get_active_lane_mask.ll b/llvm/test/Transforms/InstCombine/get_active_lane_mask.ll
new file mode 100644
index 0000000000000..49b37b9bc1ec8
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/get_active_lane_mask.ll
@@ -0,0 +1,54 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+
+define <vscale x 4 x i1> @rewrite_range_nxv4i1() {
+; CHECK-LABEL: define <vscale x 4 x i1> @rewrite_range_nxv4i1() {
+; CHECK-NEXT:    [[MASK:%.*]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 0, i32 3)
+; CHECK-NEXT:    ret <vscale x 4 x i1> [[MASK]]
+;
+  %mask = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 1, i32 4)
+  ret <vscale x 4 x i1> %mask
+}
+
+define <vscale x 16 x i1> @rewrite_range_nxv16i1() {
+; CHECK-LABEL: define <vscale x 16 x i1> @rewrite_range_nxv16i1() {
+; CHECK-NEXT:    [[MASK:%.*]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 0, i64 7)
+; CHECK-NEXT:    ret <vscale x 16 x i1> [[MASK]]
+;
+  %mask = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 123123, i64 123130)
+  ret <vscale x 16 x i1> %mask
+}
+
+define <vscale x 16 x i1> @rewrite_range_nxv16i1_i128() {
+; CHECK-LABEL: define <vscale x 16 x i1> @rewrite_range_nxv16i1_i128() {
+; CHECK-NEXT:    [[MASK:%.*]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i128(i128 0, i128 10)
+; CHECK-NEXT:    ret <vscale x 16 x i1> [[MASK]]
+;
+  %mask = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i128(i128 18446744073709551616, i128 18446744073709551626)
+  ret <vscale x 16 x i1> %mask
+}
+
+define <vscale x 4 x i1> @bail_lhs_is_zero() {
+; CHECK-LABEL: define <vscale x 4 x i1> @bail_lhs_is_zero() {
+; CHECK-NEXT:    [[MASK:%.*]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 0, i32 4)
+; CHECK-NEXT:    ret <vscale x 4 x i1> [[MASK]]
+;
+  %mask = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 0, i32 4)
+  ret <vscale x 4 x i1> %mask
+}
+
+define <vscale x 4 x i1> @lhs_gt_rhs() {
+; CHECK-LABEL: define <vscale x 4 x i1> @lhs_gt_rhs() {
+; CHECK-NEXT:    ret <vscale x 4 x i1> zeroinitializer
+;
+  %mask = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 5, i32 4)
+  ret <vscale x 4 x i1> %mask
+}
+
+define <vscale x 4 x i1> @lhs_eq_rhs() {
+; CHECK-LABEL: define <vscale x 4 x i1> @lhs_eq_rhs() {
+; CHECK-NEXT:    ret <vscale x 4 x i1> zeroinitializer
+;
+  %mask = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 4, i32 4)
+  ret <vscale x 4 x i1> %mask
+}