[llvm] [AArch64] Combine signext_inreg of setcc(... != splat(0)) (PR #157665)

[Hari Limaye via llvm-commits]

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@@ -26097,6 +26097,17 @@ static SDValue performSetCCPunpkCombine(SDNode *N, SelectionDAG &DAG) {
   return SDValue();
 }
 
+static bool isSignExtInReg(const SDValue &V) {
+  if (V.getOpcode() != AArch64ISD::VASHR ||
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hazzlim wrote:

Oh yes this is a nice approach and I can see that the throughput is better for AND on e.g. Neoverse V2 from the SWOG.

My one thought is - do we care about paying the cost of the additional `MOVI #1` for the higher throughput AND? I think that on newer cores e.g. Neoverse V3 the throughput of SHL is equal to AND so maybe there we would favor just the SHL? Obviously there are more e.g. Neoverse V2 cores in the wild at present so I can see it would make sense to favor this, I'm just flagging this up!

https://github.com/llvm/llvm-project/pull/157665