[llvm] [AArch64] Combine signext_inreg of setcc(... != splat(0)) (PR #157665)

[Hari Limaye via llvm-commits]

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@@ -26097,6 +26097,17 @@ static SDValue performSetCCPunpkCombine(SDNode *N, SelectionDAG &DAG) {
   return SDValue();
 }
 
+static bool isSignExtInReg(const SDValue &V) {
+  if (V.getOpcode() != AArch64ISD::VASHR ||
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hazzlim wrote:

Ah yes that seems like a neat solution! 

This will leave us not catching the CTTZ_ELTS case, but that can be handled separately - I think we'd still need something along the lines of
```
  //    setcc_merge_zero(
  //       pred, insert_subvector(undef, signext_inreg(vNi1 x), 0), != splat(0))
  // => setcc_merge_zero(
  //       pred, insert_subvector(undef, x, 0), != splat(0))
```
for that one. Unless we did something when we expand the cttz.elts intrinsic perhaps, although I'm not sure how feasible that is

https://github.com/llvm/llvm-project/pull/157665