[llvm] [AArch64] Use unsigned variant of `<s|u>addv_64` SVE vector reduction intrinsic for 64 bit values (PR #157418)

[Rajveer Singh Bharadwaj via llvm-commits]

Rajveer100 wrote:

> I think it should be something like `if (N->getOperand(2).getValueType().getVectorElementType() == MVT::i64)`
> 
> 
> 
> Can you add a test case from #157122?

I thought we probably don't need the check.

https://github.com/llvm/llvm-project/pull/157418