[llvm] [AArch64] Use unsigned variant of `<s|u>addv_64` SVE vector reduction intrinsic for 64 bit values (PR #157418)

[David Green via llvm-commits]

https://github.com/davemgreen commented:

I think it should be something like `if (N->getOperand(2).getValueType().getVectorElementType() == MVT::i64)`

Can you add a test case from #157122?

https://github.com/llvm/llvm-project/pull/157418