[llvm] cc5d636 - [RISCV] Add PseudoCCANDN/ORN/XNOR to isSignExtendedW.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2025-09-05T13:06:35-07:00
New Revision: cc5d636134ae1c07338703a8f08bd82e9f56a04a

URL: https://github.com/llvm/llvm-project/commit/cc5d636134ae1c07338703a8f08bd82e9f56a04a
DIFF: https://github.com/llvm/llvm-project/commit/cc5d636134ae1c07338703a8f08bd82e9f56a04a.diff

LOG: [RISCV] Add PseudoCCANDN/ORN/XNOR to isSignExtendedW.

This matches PseudoCCAND/OR/XOR

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
index d4344416a0fef..badc111118727 100644
--- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
@@ -568,6 +568,9 @@ static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST,
     case RISCV::PseudoCCAND:
     case RISCV::PseudoCCOR:
     case RISCV::PseudoCCXOR:
+    case RISCV::PseudoCCANDN:
+    case RISCV::PseudoCCORN:
+    case RISCV::PseudoCCXNOR:
     case RISCV::PHI: {
       // If all incoming values are sign-extended, the output of AND, OR, XOR,
       // MIN, MAX, or PHI is also sign-extended.
@@ -590,6 +593,9 @@ static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST,
       case RISCV::PseudoCCAND:
       case RISCV::PseudoCCOR:
       case RISCV::PseudoCCXOR:
+      case RISCV::PseudoCCANDN:
+      case RISCV::PseudoCCORN:
+      case RISCV::PseudoCCXNOR:
         B = 4;
         E = 7;
         break;